Abstract

Resistive random access memory (ReRAM) technology is an emerging candidate for next-generation nonvolatile memory (NVM) architecture due to its simple structure, low programming voltage, fast switching speed, high on/off ratio, excellent scalability, good endurance, and great compatibility with silicon CMOS technology. The most attractive of the characteristics of ReRAM is its cross-point structure, which features a 4F2 cell size. In a cross-point structure, the existence of sneak current and resulting voltage loss due to the wire's resistance might cause read and write failures if not designed properly. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this article, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure types on the reliability of the cross-point array. We also propose an error-resilient architecture, which avoids unnecessary writes in the hard error detection unit. Assuming constant soft error rate, our approach can extend the lifetime of ReRAM up to 75% over a design without hard error detection and up to 12% over the design with a "write-verify" detection mechanism. Our approach yields greater significant lifetime improvement when considering postcycling retention degradation.

Original languageEnglish (US)
Article numberA63
JournalACM Transactions on Design Automation of Electronic Systems
Volume20
Issue number4
DOIs
StatePublished - Sep 1 2015

Fingerprint

Data storage equipment
Error detection
Memory architecture
Electric potential
Scalability
Durability
Wire
Degradation
Silicon

Keywords

  • Cross-point structure
  • Endurance failure
  • Resistive memory
  • Soft error

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Impact of cell failure on reliable cross-point resistive memory design. / Xu, Cong; Niu, Dimin; Zheng, Yang; Yu, Shimeng; Xie, Yuan.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, A63, 01.09.2015.

Research output: Contribution to journalArticle

Xu, Cong ; Niu, Dimin ; Zheng, Yang ; Yu, Shimeng ; Xie, Yuan. / Impact of cell failure on reliable cross-point resistive memory design. In: ACM Transactions on Design Automation of Electronic Systems. 2015 ; Vol. 20, No. 4.
@article{1c3d2f5e04794e52a533a3cba1966537,
title = "Impact of cell failure on reliable cross-point resistive memory design",
abstract = "Resistive random access memory (ReRAM) technology is an emerging candidate for next-generation nonvolatile memory (NVM) architecture due to its simple structure, low programming voltage, fast switching speed, high on/off ratio, excellent scalability, good endurance, and great compatibility with silicon CMOS technology. The most attractive of the characteristics of ReRAM is its cross-point structure, which features a 4F2 cell size. In a cross-point structure, the existence of sneak current and resulting voltage loss due to the wire's resistance might cause read and write failures if not designed properly. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this article, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure types on the reliability of the cross-point array. We also propose an error-resilient architecture, which avoids unnecessary writes in the hard error detection unit. Assuming constant soft error rate, our approach can extend the lifetime of ReRAM up to 75{\%} over a design without hard error detection and up to 12{\%} over the design with a {"}write-verify{"} detection mechanism. Our approach yields greater significant lifetime improvement when considering postcycling retention degradation.",
keywords = "Cross-point structure, Endurance failure, Resistive memory, Soft error",
author = "Cong Xu and Dimin Niu and Yang Zheng and Shimeng Yu and Yuan Xie",
year = "2015",
month = "9",
day = "1",
doi = "10.1145/2753759",
language = "English (US)",
volume = "20",
journal = "ACM Transactions on Design Automation of Electronic Systems",
issn = "1084-4309",
publisher = "Association for Computing Machinery (ACM)",
number = "4",

}

TY - JOUR

T1 - Impact of cell failure on reliable cross-point resistive memory design

AU - Xu, Cong

AU - Niu, Dimin

AU - Zheng, Yang

AU - Yu, Shimeng

AU - Xie, Yuan

PY - 2015/9/1

Y1 - 2015/9/1

N2 - Resistive random access memory (ReRAM) technology is an emerging candidate for next-generation nonvolatile memory (NVM) architecture due to its simple structure, low programming voltage, fast switching speed, high on/off ratio, excellent scalability, good endurance, and great compatibility with silicon CMOS technology. The most attractive of the characteristics of ReRAM is its cross-point structure, which features a 4F2 cell size. In a cross-point structure, the existence of sneak current and resulting voltage loss due to the wire's resistance might cause read and write failures if not designed properly. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this article, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure types on the reliability of the cross-point array. We also propose an error-resilient architecture, which avoids unnecessary writes in the hard error detection unit. Assuming constant soft error rate, our approach can extend the lifetime of ReRAM up to 75% over a design without hard error detection and up to 12% over the design with a "write-verify" detection mechanism. Our approach yields greater significant lifetime improvement when considering postcycling retention degradation.

AB - Resistive random access memory (ReRAM) technology is an emerging candidate for next-generation nonvolatile memory (NVM) architecture due to its simple structure, low programming voltage, fast switching speed, high on/off ratio, excellent scalability, good endurance, and great compatibility with silicon CMOS technology. The most attractive of the characteristics of ReRAM is its cross-point structure, which features a 4F2 cell size. In a cross-point structure, the existence of sneak current and resulting voltage loss due to the wire's resistance might cause read and write failures if not designed properly. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this article, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure types on the reliability of the cross-point array. We also propose an error-resilient architecture, which avoids unnecessary writes in the hard error detection unit. Assuming constant soft error rate, our approach can extend the lifetime of ReRAM up to 75% over a design without hard error detection and up to 12% over the design with a "write-verify" detection mechanism. Our approach yields greater significant lifetime improvement when considering postcycling retention degradation.

KW - Cross-point structure

KW - Endurance failure

KW - Resistive memory

KW - Soft error

UR - http://www.scopus.com/inward/record.url?scp=84942929031&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84942929031&partnerID=8YFLogxK

U2 - 10.1145/2753759

DO - 10.1145/2753759

M3 - Article

VL - 20

JO - ACM Transactions on Design Automation of Electronic Systems

JF - ACM Transactions on Design Automation of Electronic Systems

SN - 1084-4309

IS - 4

M1 - A63

ER -