TY - GEN
T1 - IMC Architecture for Robust DNN Acceleration
AU - Krishnan, Gokul
AU - Wang, Zhenyu
AU - Yang, Li
AU - Yeo, Injune
AU - Meng, Jian
AU - Joshi, Rajiv V.
AU - Cady, Nathaniel C.
AU - Fan, Deliang
AU - Seo, Jae Sun
AU - Cao, Yu
N1 - Funding Information:
In this work, we propose a novel hybrid RRAM/SRAM IMC architecture for robust DNN acceleration. The hybrid IMC architecture utilizes an RRAM IMC macro with MLC cells, an SRAM macro, and a programmable shifter. The output from the RRAM macro is compensated by the SRAM macro output to create an ensemble model and achieve bit-level compensation. The scale of compensation is controlled by using a programmable shifter for the SRAM macro output. We perform detailed experiments across different DNNs and datasets to demonstrate the performance of the proposed hybrid IMC architecture. Compared to state-of-the-art methods, the proposed hybrid IMC architecture provides a scalable solution that achieves up to 21.9%, 12.65%, and 6.5% improvement in post-mapping accuracy with minimal overhead for ResNet-20 on CIFAR-10, VGG-16 on CIFAR-10, and ResNet-18 on ImageNet, respectively. Acknowledgments This work was supported by C-BRIC, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA, and the Air Force Research Laboratory award #FA8750-19-1-0014.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - RRAM-based in-memory computing (IMC) effectively accelerates deep neural networks (DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM device variations and lower precision, the mapping of DNNs to RRAM-based IMC suffers from severe accuracy loss. In this work, we propose a novel hybrid IMC architecture that integrates an RRAM-based IMC macro with a digital SRAM macro using a programmable shifter to compensate for the RRAM variations and recover the accuracy. The digital SRAM macro consists of a small SRAM memory array and an array of multiply-and-accumulate (MAC) units. The non-ideal output from the RRAM macro, due to device and circuit nonidealities, is compensated by adding the precise output from the SRAM macro. In addition, the programmable shifter allows for different scales of compensation by shifting the SRAM macro output relative to the RRAM macro output. We design a silicon prototype of the proposed hybrid IMC architecture in the 65nm SUNY process to demonstrate its efficacy. Experimental evaluation of the hybrid IMC architecture shows up to 21.9%, and 6.5% improvement in post-mapping accuracy over state-of-the-art techniques, at minimal overhead for CIFAR-10 and ImageNet datasets, respectively.
AB - RRAM-based in-memory computing (IMC) effectively accelerates deep neural networks (DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM device variations and lower precision, the mapping of DNNs to RRAM-based IMC suffers from severe accuracy loss. In this work, we propose a novel hybrid IMC architecture that integrates an RRAM-based IMC macro with a digital SRAM macro using a programmable shifter to compensate for the RRAM variations and recover the accuracy. The digital SRAM macro consists of a small SRAM memory array and an array of multiply-and-accumulate (MAC) units. The non-ideal output from the RRAM macro, due to device and circuit nonidealities, is compensated by adding the precise output from the SRAM macro. In addition, the programmable shifter allows for different scales of compensation by shifting the SRAM macro output relative to the RRAM macro output. We design a silicon prototype of the proposed hybrid IMC architecture in the 65nm SUNY process to demonstrate its efficacy. Experimental evaluation of the hybrid IMC architecture shows up to 21.9%, and 6.5% improvement in post-mapping accuracy over state-of-the-art techniques, at minimal overhead for CIFAR-10 and ImageNet datasets, respectively.
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U2 - 10.1109/ICSICT55466.2022.9963165
DO - 10.1109/ICSICT55466.2022.9963165
M3 - Conference contribution
AN - SCOPUS:85143970044
T3 - Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022
BT - Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022
A2 - Ye, Fan
A2 - Tang, Ting-Ao
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022
Y2 - 25 October 2022 through 28 October 2022
ER -