ILP and heuristic techniques for system-level design on network processor architectures

Chris Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

Original languageEnglish (US)
Article number48
JournalACM Transactions on Design Automation of Electronic Systems
Volume12
Issue number4
DOIs
StatePublished - Sep 1 2007

Fingerprint

Inductive logic programming (ILP)
Linear programming
Throughput
Data storage equipment
Processing

Keywords

  • Block multithreading
  • Multiprocessor

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

ILP and heuristic techniques for system-level design on network processor architectures. / Ostler, Chris; Chatha, Karam S.; Ramamurthi, Vijay; Srinivasan, Krishnan.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, 48, 01.09.2007.

Research output: Contribution to journalArticle

Ostler, Chris ; Chatha, Karam S. ; Ramamurthi, Vijay ; Srinivasan, Krishnan. / ILP and heuristic techniques for system-level design on network processor architectures. In: ACM Transactions on Design Automation of Electronic Systems. 2007 ; Vol. 12, No. 4.
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