ILP and heuristic techniques for system-level design on network processor architectures

Chris Ostler; Karam S. Chatha; Vijay Ramamurthi; Krishnan Srinivasan

doi:10.1145/1278349.1278361

ILP and heuristic techniques for system-level design on network processor architectures

Chris Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

Original language	English (US)
Article number	48
Journal	ACM Transactions on Design Automation of Electronic Systems
Volume	12
Issue number	4
DOIs	https://doi.org/10.1145/1278349.1278361
State	Published - Sep 1 2007

Keywords

Block multithreading
Multiprocessor

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1145/1278349.1278361

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AU - Chatha, Karam S.

AU - Ramamurthi, Vijay

AU - Srinivasan, Krishnan

PY - 2007/9/1

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N2 - Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

AB - Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

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ILP and heuristic techniques for system-level design on network processor architectures

Abstract

Keywords

ASJC Scopus subject areas

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