Hybrid network on chip (HNoC): Local buses with a global mesh architecture

Payman Zarkesh-Ha, George B.P. Bezerra, Stephanie Forrest, Melanie Moses

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

Network on chip (NoC) is often implemented with packetbased communication rather than bus connections between cores. Although NoC is a good solution for long-distance communication, local buses are more efficient for short-distance connections. In this paper, we propose a hybrid network on chip (HNoC) fabric that uses local buses for nearest-neighbor communication and the standard NoC topology for global interconnection. Local buses carry all the nearest-neighbor traffic, reducing traffic on the global network, which results in increased throughput and reduced energy consumption. Based on a communication probability density (CPD) function derived from Rent's rule, it is shown that in a 25-core chip multiprocessor, HNoC can remove up to 78% of the traffic from the global NoC topology, which results in 4.6x higher throughput and a 58% reduction in energy consumption compared to a conventional NoC topology.

Original languageEnglish (US)
Title of host publicationSLIP'10 - Proceedings of the 2010 Workshop on System Level Interconnect Prediction
Pages9-14
Number of pages6
DOIs
StatePublished - Jul 30 2010
Externally publishedYes
Event12th ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP'10 - Anaheim, CA, United States
Duration: Jun 13 2010Jun 13 2010

Other

Other12th ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP'10
CountryUnited States
CityAnaheim, CA
Period6/13/106/13/10

Fingerprint

Mesh
Communication
Topology
Traffic
Energy Consumption
Nearest Neighbor
Energy utilization
Throughput
Chip multiprocessors
Architecture
Network on chip
Network-on-chip
Interconnection
Probability density function
High Throughput

Keywords

  • Global mesh
  • Hybrid network on chip
  • Local buses
  • Network traffic
  • Stochastic model
  • Throughput

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

Cite this

Zarkesh-Ha, P., Bezerra, G. B. P., Forrest, S., & Moses, M. (2010). Hybrid network on chip (HNoC): Local buses with a global mesh architecture. In SLIP'10 - Proceedings of the 2010 Workshop on System Level Interconnect Prediction (pp. 9-14) https://doi.org/10.1145/1811100.1811104

Hybrid network on chip (HNoC) : Local buses with a global mesh architecture. / Zarkesh-Ha, Payman; Bezerra, George B.P.; Forrest, Stephanie; Moses, Melanie.

SLIP'10 - Proceedings of the 2010 Workshop on System Level Interconnect Prediction. 2010. p. 9-14.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zarkesh-Ha, P, Bezerra, GBP, Forrest, S & Moses, M 2010, Hybrid network on chip (HNoC): Local buses with a global mesh architecture. in SLIP'10 - Proceedings of the 2010 Workshop on System Level Interconnect Prediction. pp. 9-14, 12th ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP'10, Anaheim, CA, United States, 6/13/10. https://doi.org/10.1145/1811100.1811104
Zarkesh-Ha P, Bezerra GBP, Forrest S, Moses M. Hybrid network on chip (HNoC): Local buses with a global mesh architecture. In SLIP'10 - Proceedings of the 2010 Workshop on System Level Interconnect Prediction. 2010. p. 9-14 https://doi.org/10.1145/1811100.1811104
Zarkesh-Ha, Payman ; Bezerra, George B.P. ; Forrest, Stephanie ; Moses, Melanie. / Hybrid network on chip (HNoC) : Local buses with a global mesh architecture. SLIP'10 - Proceedings of the 2010 Workshop on System Level Interconnect Prediction. 2010. pp. 9-14
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