TY - JOUR
T1 - Hybrid interleaved space vector PWM for ripple reduction in modular converters
AU - Mao, Xiaolin
AU - Jain, Amit Kumar
AU - Ayyanar, Raja
N1 - Funding Information:
Manuscript received January 27, 2010; revised June 15, 2010 and August 20, 2010; accepted November 18, 2010. Date of current version August 5, 2011. This work was supported in part by the Peregrine Power LLC and Office of Naval Research under Grant N00014-08-C-0253. Recommended for publication by Associate Editor B. Wu. X. Mao and R. Ayyanar are with Arizona State University, Tempe, AZ 85287 USA (e-mail: xiaolin.mao@asu.edu; rayyanar@asu.edu). A. K. Jain is with Peregrine Power LLC, Wilsonville, OR 97070 USA (e-mail: ajain@peregrinepower.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2010.2098048
PY - 2011
Y1 - 2011
N2 - This paper addresses the problem of optimizing space vector PWM (SVM) for interleaved, parallel-connected, three-phase voltage source converters to reduce total harmonic distortion (THD) of the total line current. A systematic approach is presented for designing hybrid SVM schemes involving multiple sequences, including those based on active state division, and different phase shifts to reduce current ripple. First, the effect of different phase shifts on the current ripple is investigated and it is shown that using standard phase shifts yields performance close to optimal. Second, a zone-division plot is generated based on all sequence-phase shift combinations. The plot shows spatial regions within a sector where a certain sequence-phase shift combination results in the lowest rms current ripple in one switching period, and thus represents the optimal hybrid scheme. Lastly, simplified, easy-to-implement quasi-optimal SVM schemes are derived from the zone-division plot based on specific application requirements, and their performances are compared with the optimal scheme. The application of the proposed approach to a two-converter case is discussed in detail. A simple, quasi-optimal SVM scheme is proposed for grid-connected applications with analytical and experimental results confirming significant reduction in current THD. Finally, extension to three-and four-converter cases is discussed.
AB - This paper addresses the problem of optimizing space vector PWM (SVM) for interleaved, parallel-connected, three-phase voltage source converters to reduce total harmonic distortion (THD) of the total line current. A systematic approach is presented for designing hybrid SVM schemes involving multiple sequences, including those based on active state division, and different phase shifts to reduce current ripple. First, the effect of different phase shifts on the current ripple is investigated and it is shown that using standard phase shifts yields performance close to optimal. Second, a zone-division plot is generated based on all sequence-phase shift combinations. The plot shows spatial regions within a sector where a certain sequence-phase shift combination results in the lowest rms current ripple in one switching period, and thus represents the optimal hybrid scheme. Lastly, simplified, easy-to-implement quasi-optimal SVM schemes are derived from the zone-division plot based on specific application requirements, and their performances are compared with the optimal scheme. The application of the proposed approach to a two-converter case is discussed in detail. A simple, quasi-optimal SVM scheme is proposed for grid-connected applications with analytical and experimental results confirming significant reduction in current THD. Finally, extension to three-and four-converter cases is discussed.
KW - Harmonic distortion
KW - hybrid PWM
KW - interleaving
KW - pulse width modulation (PWM)
KW - space vector
KW - switching sequences
KW - three-phase inverters
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U2 - 10.1109/TPEL.2010.2098048
DO - 10.1109/TPEL.2010.2098048
M3 - Article
AN - SCOPUS:80051679052
SN - 0885-8993
VL - 26
SP - 1954
EP - 1967
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 7
M1 - 5659913
ER -