High-speed, low-voltage complementary heterostructure FET circuit technology

Richard Kiehl, J. Yates, L. F. Palmateer, S. L. Wright, D. J. Frank, T. N. Jackson, J. F. Degelormo, A. J. Fleischman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs/GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 μm gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.

Original languageEnglish (US)
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
PublisherPubl by IEEE
Pages101-104
Number of pages4
ISBN (Print)078030196X
StatePublished - Jan 1992
Externally publishedYes
Event13th Annual GaAs IC Symposium Technical Digest - Monterey, CA, USA
Duration: Oct 20 1991Oct 23 1991

Other

Other13th Annual GaAs IC Symposium Technical Digest
CityMonterey, CA, USA
Period10/20/9110/23/91

Fingerprint

Field effect transistors
Heterojunctions
Networks (circuits)
Electric potential
Semiconductor quantum wells
Fabrication
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kiehl, R., Yates, J., Palmateer, L. F., Wright, S. L., Frank, D. J., Jackson, T. N., ... Fleischman, A. J. (1992). High-speed, low-voltage complementary heterostructure FET circuit technology. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 101-104). Publ by IEEE.

High-speed, low-voltage complementary heterostructure FET circuit technology. / Kiehl, Richard; Yates, J.; Palmateer, L. F.; Wright, S. L.; Frank, D. J.; Jackson, T. N.; Degelormo, J. F.; Fleischman, A. J.

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, 1992. p. 101-104.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kiehl, R, Yates, J, Palmateer, LF, Wright, SL, Frank, DJ, Jackson, TN, Degelormo, JF & Fleischman, AJ 1992, High-speed, low-voltage complementary heterostructure FET circuit technology. in Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, pp. 101-104, 13th Annual GaAs IC Symposium Technical Digest, Monterey, CA, USA, 10/20/91.
Kiehl R, Yates J, Palmateer LF, Wright SL, Frank DJ, Jackson TN et al. High-speed, low-voltage complementary heterostructure FET circuit technology. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE. 1992. p. 101-104
Kiehl, Richard ; Yates, J. ; Palmateer, L. F. ; Wright, S. L. ; Frank, D. J. ; Jackson, T. N. ; Degelormo, J. F. ; Fleischman, A. J. / High-speed, low-voltage complementary heterostructure FET circuit technology. Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, 1992. pp. 101-104
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