High sample rate systolic architectures for median filters

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

This paper presents high sample rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both the cases consists of a linear systolic array of processors. The computations in each processor are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window Wi and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window Wi-1 simultaneously.

Original languageEnglish (US)
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1073-1076
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - Jan 1 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: May 10 1992May 13 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period5/10/925/13/92

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Chakrabarti, C. (1992). High sample rate systolic architectures for median filters. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 (pp. 1073-1076). [230294] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.1992.230294