High sample rate systolic architectures for median filters

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents high sample rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both the cases consists of a linear systolic array of processors. The computations in each processor are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window Wi and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window Wi-1 simultaneously.

Original languageEnglish (US)
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1073-1076
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - Jan 1 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: May 10 1992May 13 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period5/10/925/13/92

Fingerprint

Systolic arrays
Median filters
Sorting

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Chakrabarti, C. (1992). High sample rate systolic architectures for median filters. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 (pp. 1073-1076). [230294] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.1992.230294

High sample rate systolic architectures for median filters. / Chakrabarti, Chaitali.

1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1073-1076 230294 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chakrabarti, C 1992, High sample rate systolic architectures for median filters. in 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992., 230294, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1073-1076, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992, San Diego, United States, 5/10/92. https://doi.org/10.1109/ISCAS.1992.230294
Chakrabarti C. High sample rate systolic architectures for median filters. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 1073-1076. 230294. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.1992.230294
Chakrabarti, Chaitali. / High sample rate systolic architectures for median filters. 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 1073-1076 (Proceedings - IEEE International Symposium on Circuits and Systems).
@inproceedings{79a463cc0229400a854da65d81f3731b,
title = "High sample rate systolic architectures for median filters",
abstract = "This paper presents high sample rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both the cases consists of a linear systolic array of processors. The computations in each processor are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window Wi and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window Wi-1 simultaneously.",
author = "Chaitali Chakrabarti",
year = "1992",
month = "1",
day = "1",
doi = "10.1109/ISCAS.1992.230294",
language = "English (US)",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1073--1076",
booktitle = "1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992",

}

TY - GEN

T1 - High sample rate systolic architectures for median filters

AU - Chakrabarti, Chaitali

PY - 1992/1/1

Y1 - 1992/1/1

N2 - This paper presents high sample rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both the cases consists of a linear systolic array of processors. The computations in each processor are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window Wi and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window Wi-1 simultaneously.

AB - This paper presents high sample rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both the cases consists of a linear systolic array of processors. The computations in each processor are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window Wi and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window Wi-1 simultaneously.

UR - http://www.scopus.com/inward/record.url?scp=33747655334&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33747655334&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.1992.230294

DO - 10.1109/ISCAS.1992.230294

M3 - Conference contribution

AN - SCOPUS:33747655334

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1073

EP - 1076

BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992

PB - Institute of Electrical and Electronics Engineers Inc.

ER -