High sample rate systolic architectures for median filters

Chaitali Chakrabarti

doi:10.1109/ISCAS.1992.230294

High sample rate systolic architectures for median filters

Chaitali Chakrabarti

Engineering, Ira A. Fulton Schools of (IAFSE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

This paper presents high sample rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both the cases consists of a linear systolic array of processors. The computations in each processor are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window Wi and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window Wi-1 simultaneously.

Original language	English (US)
Title of host publication	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1073-1076
Number of pages	4
ISBN (Electronic)	0780305930
DOIs	https://doi.org/10.1109/ISCAS.1992.230294
State	Published - 1992
Event	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States Duration: May 10 1992 → May 13 1992

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
ISSN (Print)	0271-4310

Conference

Conference	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Country/Territory	United States
City	San Diego
Period	5/10/92 → 5/13/92

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.1992.230294

Cite this

High sample rate systolic architectures for median filters. / Chakrabarti, Chaitali.
1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1073-1076 230294 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chakrabarti, C 1992, High sample rate systolic architectures for median filters. in 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992., 230294, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1073-1076, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992, San Diego, United States, 5/10/92. https://doi.org/10.1109/ISCAS.1992.230294

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AB - This paper presents high sample rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both the cases consists of a linear systolic array of processors. The computations in each processor are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window Wi and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window Wi-1 simultaneously.

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M3 - Conference contribution

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ER -

High sample rate systolic architectures for median filters

Abstract

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