This correspondence presents high sample rate semi-systolic array architectures for computing 1-D and 2-D nonrecursive and recursive median filters. A high sample rate is obtained by pipelining the computations in each processor. Although the nonrecursive filters are pipelined by placing latches in the feedforward paths, the recursive filters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches.
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering