TY - GEN
T1 - High Sample rate architectures for median filters
AU - Chakrabarti, Chaitali
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - This paper presents high sample rate array architectures and sorting network-based architectures for computing both recursive and non-recursive median niters. The proposed array architectures have a sampling rate that is higher than that of existing architectures. This is achieved by pipelining the computations in each processor. While the non-recursive niters are pipelined by placing latches in the feed-forward paths, the recursive niters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches. The proposed sorting network-based architectures are highly pipelined, and consist of fewer compare-swap units than existing architectures. The reduction in the number of compare-swap units is achieved by processing multiple outputs at the same time, and also by using Batcher's odd-even merge sort. The latency of these networks is reduced by building them with sorting units which sort 2 elements (sort-S) as well as 3 elements (sort-3) in 1 time unit.
AB - This paper presents high sample rate array architectures and sorting network-based architectures for computing both recursive and non-recursive median niters. The proposed array architectures have a sampling rate that is higher than that of existing architectures. This is achieved by pipelining the computations in each processor. While the non-recursive niters are pipelined by placing latches in the feed-forward paths, the recursive niters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches. The proposed sorting network-based architectures are highly pipelined, and consist of fewer compare-swap units than existing architectures. The reduction in the number of compare-swap units is achieved by processing multiple outputs at the same time, and also by using Batcher's odd-even merge sort. The latency of these networks is reduced by building them with sorting units which sort 2 elements (sort-S) as well as 3 elements (sort-3) in 1 time unit.
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U2 - 10.1109/VLSISP.1992.641080
DO - 10.1109/VLSISP.1992.641080
M3 - Conference contribution
AN - SCOPUS:85068125485
T3 - Workshop on VLSI Signal Processing 1992
SP - 490
EP - 499
BT - Workshop on VLSI Signal Processing 1992
A2 - Przytula, Wojtek
A2 - Yao, Kung
A2 - Jain, Rajeev
A2 - Rabaey, Jan
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th IEEE Workshop on VLSI Signal Processing
Y2 - 28 October 1992 through 30 October 1992
ER -