High Sample rate architectures for median filters

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


This paper presents high sample rate array architectures and sorting network-based architectures for computing both recursive and non-recursive median niters. The proposed array architectures have a sampling rate that is higher than that of existing architectures. This is achieved by pipelining the computations in each processor. While the non-recursive niters are pipelined by placing latches in the feed-forward paths, the recursive niters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches. The proposed sorting network-based architectures are highly pipelined, and consist of fewer compare-swap units than existing architectures. The reduction in the number of compare-swap units is achieved by processing multiple outputs at the same time, and also by using Batcher's odd-even merge sort. The latency of these networks is reduced by building them with sorting units which sort 2 elements (sort-S) as well as 3 elements (sort-3) in 1 time unit.

Original languageEnglish (US)
Title of host publicationWorkshop on VLSI Signal Processing 1992
EditorsWojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Electronic)0780308115, 9780780308114
StatePublished - Jan 1 1992
Event6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
Duration: Oct 28 1992Oct 30 1992

Publication series

NameWorkshop on VLSI Signal Processing 1992


Conference6th IEEE Workshop on VLSI Signal Processing
Country/TerritoryUnited States
CityLos Angeles

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Applied Mathematics


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