Abstract
In this paper we propose a variety of architectures for implementing block adaptive filters in the time-domain. These filters are based on a block implementation of the least mean squares (BLMS) algorithm. First, we present an architecture which directly maps the BLMS algorithm into an array of processors. Next, we describe an architecture where the weight vector is updated without explicitly computing the filter error. Third, we describe an architecture which exploits the redundant computations of overlapping windows. All the architectures have a significantly smaller sample period compared to frequency domain implementations. Moreover, the sample periods can be reduced even further by applying relaxed look-ahead techniques.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | IEEE |
| Pages | 131-134 |
| Number of pages | 4 |
| Volume | 4 |
| State | Published - 1994 |
| Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: May 30 1994 → Jun 2 1994 |
Other
| Other | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) |
|---|---|
| City | London, England |
| Period | 5/30/94 → 6/2/94 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials