High sample rate architectures for block adaptive filters

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we propose a variety of architectures for implementing block adaptive filters in the time-domain. These filters are based on a block implementation of the least mean squares (BLMS) algorithm. First, we present an architecture which directly maps the BLMS algorithm into an array of processors. Next, we describe an architecture where the weight vector is updated without explicitly computing the filter error. Third, we describe an architecture which exploits the redundant computations of overlapping windows. All the architectures have a significantly smaller sample period compared to frequency domain implementations. Moreover, the sample periods can be reduced even further by applying relaxed look-ahead techniques.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages131-134
Number of pages4
Volume4
StatePublished - 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

Other

OtherProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)
CityLondon, England
Period5/30/946/2/94

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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