TY - GEN
T1 - High performance ZVT with bus clamping modulation technique for single phase full bridge inverters
AU - Xia, Yinglai
AU - Ayyanar, Raja
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/10
Y1 - 2016/5/10
N2 - This paper proposes a topology based on bus clamping modulation and zero-voltage-transition (ZVT) technique to realize zero-voltage-switching (ZVS) for all the main switches of the full bridge inverters, and inherent ZVS and/or ZCS for the auxiliary switches. The advantages of the strategy include significant reduction in the turn-on loss of the ZVT auxiliary switches which typically account for a major part of the total loss in other ZVT circuits, and reduction in the voltage ratings of auxiliary switches. The modulation scheme and the commutation stages are analyzed in detail. Finally, a 1kW, 500 kHz switching frequency inverter of the proposed topology using SiC MOSFETs has been built to validate the theoretical analysis. The ZVT with bus clamping modulation technique of fixed timing and adaptive timing schemes are implemented in DSP TMS320F28335 resulting in full ZVS for the main switches in the full bridge inverter. The proposed scheme can save up to 33 % of the switching loss compared with no ZVT case.
AB - This paper proposes a topology based on bus clamping modulation and zero-voltage-transition (ZVT) technique to realize zero-voltage-switching (ZVS) for all the main switches of the full bridge inverters, and inherent ZVS and/or ZCS for the auxiliary switches. The advantages of the strategy include significant reduction in the turn-on loss of the ZVT auxiliary switches which typically account for a major part of the total loss in other ZVT circuits, and reduction in the voltage ratings of auxiliary switches. The modulation scheme and the commutation stages are analyzed in detail. Finally, a 1kW, 500 kHz switching frequency inverter of the proposed topology using SiC MOSFETs has been built to validate the theoretical analysis. The ZVT with bus clamping modulation technique of fixed timing and adaptive timing schemes are implemented in DSP TMS320F28335 resulting in full ZVS for the main switches in the full bridge inverter. The proposed scheme can save up to 33 % of the switching loss compared with no ZVT case.
KW - ZVT
KW - bus clamping
KW - full bridge
KW - switching loss saving
UR - http://www.scopus.com/inward/record.url?scp=84973644380&partnerID=8YFLogxK
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U2 - 10.1109/APEC.2016.7468350
DO - 10.1109/APEC.2016.7468350
M3 - Conference contribution
AN - SCOPUS:84973644380
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 3364
EP - 3369
BT - 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016
Y2 - 20 March 2016 through 24 March 2016
ER -