High performance ZVT with bus clamping modulation technique for single phase full bridge inverters

Yinglai Xia; Raja Ayyanar

doi:10.1109/APEC.2016.7468350

High performance ZVT with bus clamping modulation technique for single phase full bridge inverters

Yinglai Xia, Raja Ayyanar

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Scopus citations

Abstract

This paper proposes a topology based on bus clamping modulation and zero-voltage-transition (ZVT) technique to realize zero-voltage-switching (ZVS) for all the main switches of the full bridge inverters, and inherent ZVS and/or ZCS for the auxiliary switches. The advantages of the strategy include significant reduction in the turn-on loss of the ZVT auxiliary switches which typically account for a major part of the total loss in other ZVT circuits, and reduction in the voltage ratings of auxiliary switches. The modulation scheme and the commutation stages are analyzed in detail. Finally, a 1kW, 500 kHz switching frequency inverter of the proposed topology using SiC MOSFETs has been built to validate the theoretical analysis. The ZVT with bus clamping modulation technique of fixed timing and adaptive timing schemes are implemented in DSP TMS320F28335 resulting in full ZVS for the main switches in the full bridge inverter. The proposed scheme can save up to 33 % of the switching loss compared with no ZVT case.

Original language	English (US)
Title of host publication	2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	3364-3369
Number of pages	6
Volume	2016-May
ISBN (Electronic)	9781467383936
DOIs	https://doi.org/10.1109/APEC.2016.7468350
State	Published - May 10 2016
Event	31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016 - Long Beach, United States Duration: Mar 20 2016 → Mar 24 2016

Other

Other	31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016
Country/Territory	United States
City	Long Beach
Period	3/20/16 → 3/24/16

Keywords

bus clamping
full bridge
switching loss saving
ZVT

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APEC.2016.7468350

Cite this

High performance ZVT with bus clamping modulation technique for single phase full bridge inverters. / Xia, Yinglai; Ayyanar, Raja.

2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016. Vol. 2016-May Institute of Electrical and Electronics Engineers Inc., 2016. p. 3364-3369 7468350.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Xia, Y & Ayyanar, R 2016, High performance ZVT with bus clamping modulation technique for single phase full bridge inverters. in 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016. vol. 2016-May, 7468350, Institute of Electrical and Electronics Engineers Inc., pp. 3364-3369, 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016, Long Beach, United States, 3/20/16. https://doi.org/10.1109/APEC.2016.7468350

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abstract = "This paper proposes a topology based on bus clamping modulation and zero-voltage-transition (ZVT) technique to realize zero-voltage-switching (ZVS) for all the main switches of the full bridge inverters, and inherent ZVS and/or ZCS for the auxiliary switches. The advantages of the strategy include significant reduction in the turn-on loss of the ZVT auxiliary switches which typically account for a major part of the total loss in other ZVT circuits, and reduction in the voltage ratings of auxiliary switches. The modulation scheme and the commutation stages are analyzed in detail. Finally, a 1kW, 500 kHz switching frequency inverter of the proposed topology using SiC MOSFETs has been built to validate the theoretical analysis. The ZVT with bus clamping modulation technique of fixed timing and adaptive timing schemes are implemented in DSP TMS320F28335 resulting in full ZVS for the main switches in the full bridge inverter. The proposed scheme can save up to 33 % of the switching loss compared with no ZVT case.",

keywords = "bus clamping, full bridge, switching loss saving, ZVT",

author = "Yinglai Xia and Raja Ayyanar",

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N2 - This paper proposes a topology based on bus clamping modulation and zero-voltage-transition (ZVT) technique to realize zero-voltage-switching (ZVS) for all the main switches of the full bridge inverters, and inherent ZVS and/or ZCS for the auxiliary switches. The advantages of the strategy include significant reduction in the turn-on loss of the ZVT auxiliary switches which typically account for a major part of the total loss in other ZVT circuits, and reduction in the voltage ratings of auxiliary switches. The modulation scheme and the commutation stages are analyzed in detail. Finally, a 1kW, 500 kHz switching frequency inverter of the proposed topology using SiC MOSFETs has been built to validate the theoretical analysis. The ZVT with bus clamping modulation technique of fixed timing and adaptive timing schemes are implemented in DSP TMS320F28335 resulting in full ZVS for the main switches in the full bridge inverter. The proposed scheme can save up to 33 % of the switching loss compared with no ZVT case.

AB - This paper proposes a topology based on bus clamping modulation and zero-voltage-transition (ZVT) technique to realize zero-voltage-switching (ZVS) for all the main switches of the full bridge inverters, and inherent ZVS and/or ZCS for the auxiliary switches. The advantages of the strategy include significant reduction in the turn-on loss of the ZVT auxiliary switches which typically account for a major part of the total loss in other ZVT circuits, and reduction in the voltage ratings of auxiliary switches. The modulation scheme and the commutation stages are analyzed in detail. Finally, a 1kW, 500 kHz switching frequency inverter of the proposed topology using SiC MOSFETs has been built to validate the theoretical analysis. The ZVT with bus clamping modulation technique of fixed timing and adaptive timing schemes are implemented in DSP TMS320F28335 resulting in full ZVS for the main switches in the full bridge inverter. The proposed scheme can save up to 33 % of the switching loss compared with no ZVT case.

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KW - full bridge

KW - switching loss saving

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ER -

High performance ZVT with bus clamping modulation technique for single phase full bridge inverters

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