TY - GEN
T1 - High performance thin crystalline silicon solar cell grown on silicon-on-insulator
AU - Murcia, C. Paola
AU - Hao, Ruiying
AU - Biegala, Tom
AU - Honsberg, Christiana
AU - Barnett, Allen
PY - 2009
Y1 - 2009
N2 - High open circuit voltage (Voc) is a potential benefit of thin silicon solar cells. A new thin silicon solar cell structure is proposed using silicon-on-insulator (SOI) technology that investigates the properties of high voltage in thin silicon designs with an epitaxial emitter. Key design parameters are low rear and front surface recombination, low dark current and efficient light trapping. We propose a patterned emitter area on a SOI substrate. The advantages of this design are the passivation properties embedded in the buried oxide and the reduced junction area. With a uniform epitaxial emitter, the top contact shadowing can be designed to be 0%. Preliminary results show V oc >525mV and JSC>20mA/cm2 with-anti-reflection coating. This represents a substantial increase from previous work by Danos et al. which reported Voc <500mV and JSC∼0. 45mAlcm2 [5]. This present design also demonstrates the effect of a smaller emitter area and reports higher performance parameters for reported silicon cells fabricated on SOI substrates.
AB - High open circuit voltage (Voc) is a potential benefit of thin silicon solar cells. A new thin silicon solar cell structure is proposed using silicon-on-insulator (SOI) technology that investigates the properties of high voltage in thin silicon designs with an epitaxial emitter. Key design parameters are low rear and front surface recombination, low dark current and efficient light trapping. We propose a patterned emitter area on a SOI substrate. The advantages of this design are the passivation properties embedded in the buried oxide and the reduced junction area. With a uniform epitaxial emitter, the top contact shadowing can be designed to be 0%. Preliminary results show V oc >525mV and JSC>20mA/cm2 with-anti-reflection coating. This represents a substantial increase from previous work by Danos et al. which reported Voc <500mV and JSC∼0. 45mAlcm2 [5]. This present design also demonstrates the effect of a smaller emitter area and reports higher performance parameters for reported silicon cells fabricated on SOI substrates.
UR - http://www.scopus.com/inward/record.url?scp=77951568178&partnerID=8YFLogxK
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U2 - 10.1109/PVSC.2009.5411219
DO - 10.1109/PVSC.2009.5411219
M3 - Conference contribution
AN - SCOPUS:77951568178
SN - 9781424429509
T3 - Conference Record of the IEEE Photovoltaic Specialists Conference
SP - 1137
EP - 1140
BT - 2009 34th IEEE Photovoltaic Specialists Conference, PVSC 2009
T2 - 2009 34th IEEE Photovoltaic Specialists Conference, PVSC 2009
Y2 - 7 June 2009 through 12 June 2009
ER -