High performance set associative translation lookaside buffers for low power microprocessors

Jonathan R. Haigh, Lawrence T. Clark

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.

Original languageEnglish (US)
Pages (from-to)509-523
Number of pages15
JournalIntegration, the VLSI Journal
Volume41
Issue number4
DOIs
StatePublished - Jul 2008

Fingerprint

Computer aided manufacturing
Microprocessor chips
Clocks
Energy dissipation

Keywords

  • Content addressable memory
  • Embedded memory
  • Microprocessor
  • Power dissipation
  • Register file
  • Translation lookaside buffer
  • VLSI integrated circuits

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

High performance set associative translation lookaside buffers for low power microprocessors. / Haigh, Jonathan R.; Clark, Lawrence T.

In: Integration, the VLSI Journal, Vol. 41, No. 4, 07.2008, p. 509-523.

Research output: Contribution to journalArticle

Haigh, Jonathan R. ; Clark, Lawrence T. / High performance set associative translation lookaside buffers for low power microprocessors. In: Integration, the VLSI Journal. 2008 ; Vol. 41, No. 4. pp. 509-523.
@article{fabdad442e7e42648554fd784b21527a,
title = "High performance set associative translation lookaside buffers for low power microprocessors",
abstract = "A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28{\%} lower delay and up to 50{\%} lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.",
keywords = "Content addressable memory, Embedded memory, Microprocessor, Power dissipation, Register file, Translation lookaside buffer, VLSI integrated circuits",
author = "Haigh, {Jonathan R.} and Clark, {Lawrence T.}",
year = "2008",
month = "7",
doi = "10.1016/j.vlsi.2007.11.003",
language = "English (US)",
volume = "41",
pages = "509--523",
journal = "Integration, the VLSI Journal",
issn = "0167-9260",
publisher = "Elsevier",
number = "4",

}

TY - JOUR

T1 - High performance set associative translation lookaside buffers for low power microprocessors

AU - Haigh, Jonathan R.

AU - Clark, Lawrence T.

PY - 2008/7

Y1 - 2008/7

N2 - A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.

AB - A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.

KW - Content addressable memory

KW - Embedded memory

KW - Microprocessor

KW - Power dissipation

KW - Register file

KW - Translation lookaside buffer

KW - VLSI integrated circuits

UR - http://www.scopus.com/inward/record.url?scp=43949127073&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=43949127073&partnerID=8YFLogxK

U2 - 10.1016/j.vlsi.2007.11.003

DO - 10.1016/j.vlsi.2007.11.003

M3 - Article

VL - 41

SP - 509

EP - 523

JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

SN - 0167-9260

IS - 4

ER -