High performance set associative translation lookaside buffers for low power microprocessors

Jonathan R. Haigh, Lawrence T. Clark

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.

Original languageEnglish (US)
Pages (from-to)509-523
Number of pages15
JournalIntegration, the VLSI Journal
Volume41
Issue number4
DOIs
StatePublished - Jul 1 2008

Keywords

  • Content addressable memory
  • Embedded memory
  • Microprocessor
  • Power dissipation
  • Register file
  • Translation lookaside buffer
  • VLSI integrated circuits

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'High performance set associative translation lookaside buffers for low power microprocessors'. Together they form a unique fingerprint.

  • Cite this