In this work we demonstrate high performance and low-power n-type inverters using solution-based CdS as the semiconductor in thin film transistors. Our fabrication process consists of five mask levels and a maximum temperature of 150 °C. The CdS is deposited using chemical bath deposition at 70 °C to provide full compatibility with flexible substrates. Isolated TFTs showed mobilities up to 10 cm2/V-s and threshold voltages of approximately 0.5V. Inverters were biased at 1, 3 and 5 V, resulting in maximum gains in the range of 60 at VDD = 3V. The devices and circuits are fully patterned using standard photolithographic techniques that can be used to design more complex circuitry for flexible and large area electronic applications. In addition we used an extraction parameter method for our TFTs that allows the use of regular SPICE simulation software to design and test the circuits. Our simulations are in good agreement with the experimental data for isolated devices and inverters. Other circuits such as NAND gates are also demonstrated.