High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder

Russell E. Henning; Chaitali Chakrabarti

High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder

Russell E. Henning, Chaitali Chakrabarti

IAFSE-ECEE: Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

General purpose DSPs typically used to implement speech coders in digital cellular phones do not allow enough exploitation of the speech coding algorithm itself for power reduction. In this paper, high-level design synthesis of a low power, VLIW (very long instruction word) processor dedicated to implementing the IS-54 VSELP speech encoding algorithm is presented. Significant power reduction is achieved through algorithm dependent techniques, including application specific hardware design, supply voltage reduction through highly parallel execution, and exploitation of data correlation inherent to the algorithm. Preliminary estimates indicate that the design could result in a 5.35 mm² processor that executes in real-time with an average power dissipation of about 28 mW.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Editors	Anon
Place of Publication	Piscataway, NJ, United States
Publisher	IEEE
Pages	571-576
Number of pages	6
Publication status	Published - 1997
Event	Proceedings of the 1997 International Conference on Computer Design - Austin, TX, USA Duration: Oct 12 1997 → Oct 15 1997

Other

Other	Proceedings of the 1997 International Conference on Computer Design
City	Austin, TX, USA
Period	10/12/97 → 10/15/97

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ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Henning, R. E., & Chakrabarti, C. (1997). High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. In Anon (Ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 571-576). Piscataway, NJ, United States: IEEE.

High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. / Henning, Russell E.; Chakrabarti, Chaitali.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. Piscataway, NJ, United States : IEEE, 1997. p. 571-576.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Henning, RE & Chakrabarti, C 1997, High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. in Anon (ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, Piscataway, NJ, United States, pp. 571-576, Proceedings of the 1997 International Conference on Computer Design, Austin, TX, USA, 10/12/97.

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AB - General purpose DSPs typically used to implement speech coders in digital cellular phones do not allow enough exploitation of the speech coding algorithm itself for power reduction. In this paper, high-level design synthesis of a low power, VLIW (very long instruction word) processor dedicated to implementing the IS-54 VSELP speech encoding algorithm is presented. Significant power reduction is achieved through algorithm dependent techniques, including application specific hardware design, supply voltage reduction through highly parallel execution, and exploitation of data correlation inherent to the algorithm. Preliminary estimates indicate that the design could result in a 5.35 mm2 processor that executes in real-time with an average power dissipation of about 28 mW.

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High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder

Abstract

Other

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ASJC Scopus subject areas

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