High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder

Russell E. Henning, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

General purpose DSPs typically used to implement speech coders in digital cellular phones do not allow enough exploitation of the speech coding algorithm itself for power reduction. In this paper, high-level design synthesis of a low power, VLIW (very long instruction word) processor dedicated to implementing the IS-54 VSELP speech encoding algorithm is presented. Significant power reduction is achieved through algorithm dependent techniques, including application specific hardware design, supply voltage reduction through highly parallel execution, and exploitation of data correlation inherent to the algorithm. Preliminary estimates indicate that the design could result in a 5.35 mm2 processor that executes in real-time with an average power dissipation of about 28 mW.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages571-576
Number of pages6
StatePublished - 1997
EventProceedings of the 1997 International Conference on Computer Design - Austin, TX, USA
Duration: Oct 12 1997Oct 15 1997

Other

OtherProceedings of the 1997 International Conference on Computer Design
CityAustin, TX, USA
Period10/12/9710/15/97

Fingerprint

Speech coding
Energy dissipation
Hardware
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Henning, R. E., & Chakrabarti, C. (1997). High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. In Anon (Ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 571-576). Piscataway, NJ, United States: IEEE.

High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. / Henning, Russell E.; Chakrabarti, Chaitali.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. Piscataway, NJ, United States : IEEE, 1997. p. 571-576.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Henning, RE & Chakrabarti, C 1997, High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. in Anon (ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, Piscataway, NJ, United States, pp. 571-576, Proceedings of the 1997 International Conference on Computer Design, Austin, TX, USA, 10/12/97.
Henning RE, Chakrabarti C. High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. In Anon, editor, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Piscataway, NJ, United States: IEEE. 1997. p. 571-576
Henning, Russell E. ; Chakrabarti, Chaitali. / High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP speech encoder. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. editor / Anon. Piscataway, NJ, United States : IEEE, 1997. pp. 571-576
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