High fan-in circuit design

Lawrence T. Clark, Gregory F. Taylor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A review of high fan-in circuit design in contemporary logic technologies is presented. This is followed by a description of a BiNMOS circuit structure which allows the construction of large fan-in, dynamic logical NAND or OR functions. Power and reliability considerations such as BJT reverse Vbe and MOS hot electron protection are included. Application of the circuit in the 3.3V, 100MHz, implementation of the PentiumTM Microprocessor [1] on a 0.6 mm BiNMOS process [2] is discussed.

Original languageEnglish (US)
Title of host publicationIEEE Bipolar/BiCMOS Circuits and Technology Meeting
EditorsC.R. Selvakumar
Pages27-32
Number of pages6
StatePublished - 1994
Externally publishedYes
EventProceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
Duration: Oct 10 1994Oct 11 1994

Other

OtherProceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting
CityMinneapolis, MN, USA
Period10/10/9410/11/94

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Clark, L. T., & Taylor, G. F. (1994). High fan-in circuit design. In C. R. Selvakumar (Ed.), IEEE Bipolar/BiCMOS Circuits and Technology Meeting (pp. 27-32)