High-dv/dt-immune parameter-adaptive synchronous rectifier (SR) driving scheme in high-frequency high-power-density applications

The synchronous rectifier (SR) is usually utilized to reduce the conduction loss and reverse recovery loss compared with the conventional diode bridge rectifier. However, the precise detection of the SR current zero-crossing is very challenging in high-frequency and high-power-density applications. The commercial SR drivers suffer from poor zero-crossing detection accuracy due to the device package inductance. Meanwhile, the conventional diode/FET blocking approach has over-voltage and oscillation issues during the high dv/dt transients. In this paper, a novel self-driven drain-to-source voltage sensing circuit is proposed. The circuit provides a paralleled low-impedance path to bypass the displacement current during the high dv/dt transients, which addresses the over-voltage and oscillation issues. Moreover, the adaptive SR on-time tuning algorithm is implemented, which eliminates the zero-crossing detection errors caused by the package and loop stray inductance. A 3.3 kW, 500 kHz CLLC resonant converter prototype is built to validate the proposed SR driving scheme. The prototype demonstrates the peak efficiency of 97.6% and the power density of 130 W/inch3.