High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS

Jae-sun Seo, Ron Ho, Jon Lexau, Michael Dayringer, Dennis Sylvester, David Blaauw

Research output: Chapter in Book/Report/Conference proceedingConference contribution

40 Citations (Scopus)

Abstract

Long on-chip wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter-symbol interference (ISI) [5]. Further improvements can come from equalization circuits on receivers [2] and transmitters [4] that trade off power for bandwidth. In this paper, we extend these ideas to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and show bandwidth densities of 2.2-4.4 Gb/s/μm over 90nm 5mm links, with corresponding energies of 0.24-0.34 pJ/bit on random data.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages182-183
Number of pages2
Volume53
DOIs
StatePublished - 2010
Externally publishedYes
Event2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
Duration: Feb 7 2010Feb 11 2010

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
CountryUnited States
CitySan Francisco, CA
Period2/7/102/11/10

Fingerprint

Wire
Bandwidth
Telecommunication repeaters
Networks (circuits)
FIR filters
Adaptive filters
Farms
Transmitters
Electric potential
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Seo, J., Ho, R., Lexau, J., Dayringer, M., Sylvester, D., & Blaauw, D. (2010). High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 53, pp. 182-183). [5433993] https://doi.org/10.1109/ISSCC.2010.5433993

High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. / Seo, Jae-sun; Ho, Ron; Lexau, Jon; Dayringer, Michael; Sylvester, Dennis; Blaauw, David.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 53 2010. p. 182-183 5433993.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seo, J, Ho, R, Lexau, J, Dayringer, M, Sylvester, D & Blaauw, D 2010, High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 53, 5433993, pp. 182-183, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, CA, United States, 2/7/10. https://doi.org/10.1109/ISSCC.2010.5433993
Seo J, Ho R, Lexau J, Dayringer M, Sylvester D, Blaauw D. High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 53. 2010. p. 182-183. 5433993 https://doi.org/10.1109/ISSCC.2010.5433993
Seo, Jae-sun ; Ho, Ron ; Lexau, Jon ; Dayringer, Michael ; Sylvester, Dennis ; Blaauw, David. / High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 53 2010. pp. 182-183
@inproceedings{963dbd37d1e84cbe9eb7a8e06d103eff,
title = "High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS",
abstract = "Long on-chip wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter-symbol interference (ISI) [5]. Further improvements can come from equalization circuits on receivers [2] and transmitters [4] that trade off power for bandwidth. In this paper, we extend these ideas to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and show bandwidth densities of 2.2-4.4 Gb/s/μm over 90nm 5mm links, with corresponding energies of 0.24-0.34 pJ/bit on random data.",
author = "Jae-sun Seo and Ron Ho and Jon Lexau and Michael Dayringer and Dennis Sylvester and David Blaauw",
year = "2010",
doi = "10.1109/ISSCC.2010.5433993",
language = "English (US)",
isbn = "9781424460342",
volume = "53",
pages = "182--183",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

}

TY - GEN

T1 - High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS

AU - Seo, Jae-sun

AU - Ho, Ron

AU - Lexau, Jon

AU - Dayringer, Michael

AU - Sylvester, Dennis

AU - Blaauw, David

PY - 2010

Y1 - 2010

N2 - Long on-chip wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter-symbol interference (ISI) [5]. Further improvements can come from equalization circuits on receivers [2] and transmitters [4] that trade off power for bandwidth. In this paper, we extend these ideas to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and show bandwidth densities of 2.2-4.4 Gb/s/μm over 90nm 5mm links, with corresponding energies of 0.24-0.34 pJ/bit on random data.

AB - Long on-chip wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter-symbol interference (ISI) [5]. Further improvements can come from equalization circuits on receivers [2] and transmitters [4] that trade off power for bandwidth. In this paper, we extend these ideas to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and show bandwidth densities of 2.2-4.4 Gb/s/μm over 90nm 5mm links, with corresponding energies of 0.24-0.34 pJ/bit on random data.

UR - http://www.scopus.com/inward/record.url?scp=77952170789&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77952170789&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2010.5433993

DO - 10.1109/ISSCC.2010.5433993

M3 - Conference contribution

AN - SCOPUS:77952170789

SN - 9781424460342

VL - 53

SP - 182

EP - 183

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -