Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing

Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this paper, we present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Pages126-131
Number of pages6
DOIs
StatePublished - Dec 1 2005
Externally publishedYes
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
VolumeI
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Liu, F., Flomenberg, J. J., Yasaratne, D. V., & Ozev, S. (2005). Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing. In Proceedings - Design, Automation and Test in Europe, DATE '05 (pp. 126-131). [1395542] (Proceedings -Design, Automation and Test in Europe, DATE '05; Vol. I). https://doi.org/10.1109/DATE.2005.175