Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing

Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this paper, we present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE '05
Pages126-131
Number of pages6
VolumeI
DOIs
StatePublished - 2005
Externally publishedYes
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

Fingerprint

Analog circuits
Fault tolerance
Computational efficiency
Automation
Testing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Liu, F., Flomenberg, J. J., Yasaratne, D. V., & Ozev, S. (2005). Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing. In Proceedings -Design, Automation and Test in Europe, DATE '05 (Vol. I, pp. 126-131). [1395542] https://doi.org/10.1109/DATE.2005.175

Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing. / Liu, Fang; Flomenberg, Jacob J.; Yasaratne, Devaka V.; Ozev, Sule.

Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I 2005. p. 126-131 1395542.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, F, Flomenberg, JJ, Yasaratne, DV & Ozev, S 2005, Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing. in Proceedings -Design, Automation and Test in Europe, DATE '05. vol. I, 1395542, pp. 126-131, Design, Automation and Test in Europe, DATE '05, Munich, Germany, 3/7/05. https://doi.org/10.1109/DATE.2005.175
Liu F, Flomenberg JJ, Yasaratne DV, Ozev S. Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing. In Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I. 2005. p. 126-131. 1395542 https://doi.org/10.1109/DATE.2005.175
Liu, Fang ; Flomenberg, Jacob J. ; Yasaratne, Devaka V. ; Ozev, Sule. / Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing. Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I 2005. pp. 126-131
@inproceedings{5333847c2b4d41b6ae1da2b7fbbde198,
title = "Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing",
abstract = "Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this paper, we present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.",
author = "Fang Liu and Flomenberg, {Jacob J.} and Yasaratne, {Devaka V.} and Sule Ozev",
year = "2005",
doi = "10.1109/DATE.2005.175",
language = "English (US)",
isbn = "0769522882",
volume = "I",
pages = "126--131",
booktitle = "Proceedings -Design, Automation and Test in Europe, DATE '05",

}

TY - GEN

T1 - Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing

AU - Liu, Fang

AU - Flomenberg, Jacob J.

AU - Yasaratne, Devaka V.

AU - Ozev, Sule

PY - 2005

Y1 - 2005

N2 - Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this paper, we present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

AB - Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this paper, we present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

UR - http://www.scopus.com/inward/record.url?scp=33646918905&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646918905&partnerID=8YFLogxK

U2 - 10.1109/DATE.2005.175

DO - 10.1109/DATE.2005.175

M3 - Conference contribution

AN - SCOPUS:33646918905

SN - 0769522882

SN - 0769522882

SN - 9780769522883

VL - I

SP - 126

EP - 131

BT - Proceedings -Design, Automation and Test in Europe, DATE '05

ER -