Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

Deliang Fan; Mrigank Sharad; Abhronil Sengupta; Kaushik Roy

doi:10.1109/TNNLS.2015.2462731

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

Deliang Fan, Mrigank Sharad, Abhronil Sengupta, Kaushik Roy

Research output: Contribution to journal › Article › peer-review

43 Scopus citations

Abstract

Hierarchical temporal memory (HTM) tries to mimic the computing in cerebral neocortex. It identifies spatial and temporal patterns in the input for making inferences. This may require a large number of computationally expensive tasks, such as dot product evaluations. Nanodevices that can provide direct mapping for such primitives are of great interest. In this paper, we propose that the computing blocks for HTM can be mapped using low-voltage, magnetometallic spin-neurons combined with an emerging resistive crossbar network, which involves a comprehensive design at algorithm, architecture, circuit, and device levels. Simulation results show the possibility of more than 200× lower energy as compared with a 45-nm CMOS ASIC design.

Original language	English (US)
Article number	5962385
Pages (from-to)	1907-1919
Number of pages	13
Journal	IEEE Transactions on Neural Networks and Learning Systems
Volume	27
Issue number	9
DOIs	https://doi.org/10.1109/TNNLS.2015.2462731
State	Published - Sep 2016
Externally published	Yes

Keywords

Hierarchical temporal memory (HTM)
magnetic domain walls (DWs)
memristors
neural network hardware
spin Hall effect (SHE)
spin transfer torque

ASJC Scopus subject areas

Software
Computer Science Applications
Computer Networks and Communications
Artificial Intelligence

Access to Document

10.1109/TNNLS.2015.2462731

Cite this

@article{bccf90eb249647cb86f006fc11712a14,

title = "Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing",

abstract = "Hierarchical temporal memory (HTM) tries to mimic the computing in cerebral neocortex. It identifies spatial and temporal patterns in the input for making inferences. This may require a large number of computationally expensive tasks, such as dot product evaluations. Nanodevices that can provide direct mapping for such primitives are of great interest. In this paper, we propose that the computing blocks for HTM can be mapped using low-voltage, magnetometallic spin-neurons combined with an emerging resistive crossbar network, which involves a comprehensive design at algorithm, architecture, circuit, and device levels. Simulation results show the possibility of more than 200× lower energy as compared with a 45-nm CMOS ASIC design.",

keywords = "Hierarchical temporal memory (HTM), magnetic domain walls (DWs), memristors, neural network hardware, spin Hall effect (SHE), spin transfer torque",

author = "Deliang Fan and Mrigank Sharad and Abhronil Sengupta and Kaushik Roy",

note = "Publisher Copyright: {\textcopyright} 2012 IEEE.",

year = "2016",

month = sep,

doi = "10.1109/TNNLS.2015.2462731",

language = "English (US)",

volume = "27",

pages = "1907--1919",

journal = "IEEE Transactions on Neural Networks and Learning Systems",

issn = "2162-237X",

publisher = "IEEE Computational Intelligence Society",

number = "9",

}

TY - JOUR

T1 - Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

AU - Fan, Deliang

AU - Sharad, Mrigank

AU - Sengupta, Abhronil

AU - Roy, Kaushik

PY - 2016/9

Y1 - 2016/9

N2 - Hierarchical temporal memory (HTM) tries to mimic the computing in cerebral neocortex. It identifies spatial and temporal patterns in the input for making inferences. This may require a large number of computationally expensive tasks, such as dot product evaluations. Nanodevices that can provide direct mapping for such primitives are of great interest. In this paper, we propose that the computing blocks for HTM can be mapped using low-voltage, magnetometallic spin-neurons combined with an emerging resistive crossbar network, which involves a comprehensive design at algorithm, architecture, circuit, and device levels. Simulation results show the possibility of more than 200× lower energy as compared with a 45-nm CMOS ASIC design.

AB - Hierarchical temporal memory (HTM) tries to mimic the computing in cerebral neocortex. It identifies spatial and temporal patterns in the input for making inferences. This may require a large number of computationally expensive tasks, such as dot product evaluations. Nanodevices that can provide direct mapping for such primitives are of great interest. In this paper, we propose that the computing blocks for HTM can be mapped using low-voltage, magnetometallic spin-neurons combined with an emerging resistive crossbar network, which involves a comprehensive design at algorithm, architecture, circuit, and device levels. Simulation results show the possibility of more than 200× lower energy as compared with a 45-nm CMOS ASIC design.

KW - Hierarchical temporal memory (HTM)

KW - magnetic domain walls (DWs)

KW - memristors

KW - neural network hardware

KW - spin Hall effect (SHE)

KW - spin transfer torque

UR - http://www.scopus.com/inward/record.url?scp=84939427824&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84939427824&partnerID=8YFLogxK

U2 - 10.1109/TNNLS.2015.2462731

DO - 10.1109/TNNLS.2015.2462731

M3 - Article

C2 - 26285225

AN - SCOPUS:84939427824

SN - 2162-237X

VL - 27

SP - 1907

EP - 1919

JO - IEEE Transactions on Neural Networks and Learning Systems

JF - IEEE Transactions on Neural Networks and Learning Systems

IS - 9

M1 - 5962385

ER -

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this