Hierarchical simulation approaches for the design of ultra-fast amplifier circuits

J. Desai, S. Aboud, P. Chiney, P. Osuch, J. Branlard, Stephen Goodnick, Marco Saraniti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The silicon-on-insulator (SOI) technology is one of the most promising technologies as the semiconductor industry shifts to 0.13μm and smaller devices. Fully depleted (FD) SOI transistors offer a nearly ideal behavior for application in analog circuits, particularly in high frequency and low power operation. In this work, the design and development of a highly efficient power amplifier circuit is investigated for SOI technology. A fully depleted NMOS SOI transistor is built and characterized, which exhibits TeraHertz cutoff frequencies. The device parameters of this transistor are then extracted to build a compact circuit model for use in the PSPICE circuit simulator. Finally, a low power and high frequency class E power amplifier is designed based on the SOI transistor, and a full analysis of the performance compared to bulk Si technology is performed.

Original languageEnglish (US)
Title of host publication2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
EditorsM. Laudon, B. Romanowicz
Pages33-36
Number of pages4
Volume2
StatePublished - 2004
Event2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 - Boston, MA, United States
Duration: Mar 7 2004Mar 11 2004

Other

Other2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
CountryUnited States
CityBoston, MA
Period3/7/043/11/04

Fingerprint

Transistors
Silicon on insulator technology
Networks (circuits)
Power amplifiers
Silicon
Analog circuits
Cutoff frequency
SPICE
Simulators
Semiconductor materials
Industry

Keywords

  • Class
  • Drift diffusion
  • DST
  • FDSOI
  • Power-added-efficiency

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Desai, J., Aboud, S., Chiney, P., Osuch, P., Branlard, J., Goodnick, S., & Saraniti, M. (2004). Hierarchical simulation approaches for the design of ultra-fast amplifier circuits. In M. Laudon, & B. Romanowicz (Eds.), 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 (Vol. 2, pp. 33-36)

Hierarchical simulation approaches for the design of ultra-fast amplifier circuits. / Desai, J.; Aboud, S.; Chiney, P.; Osuch, P.; Branlard, J.; Goodnick, Stephen; Saraniti, Marco.

2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004. ed. / M. Laudon; B. Romanowicz. Vol. 2 2004. p. 33-36.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Desai, J, Aboud, S, Chiney, P, Osuch, P, Branlard, J, Goodnick, S & Saraniti, M 2004, Hierarchical simulation approaches for the design of ultra-fast amplifier circuits. in M Laudon & B Romanowicz (eds), 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004. vol. 2, pp. 33-36, 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004, Boston, MA, United States, 3/7/04.
Desai J, Aboud S, Chiney P, Osuch P, Branlard J, Goodnick S et al. Hierarchical simulation approaches for the design of ultra-fast amplifier circuits. In Laudon M, Romanowicz B, editors, 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004. Vol. 2. 2004. p. 33-36
Desai, J. ; Aboud, S. ; Chiney, P. ; Osuch, P. ; Branlard, J. ; Goodnick, Stephen ; Saraniti, Marco. / Hierarchical simulation approaches for the design of ultra-fast amplifier circuits. 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004. editor / M. Laudon ; B. Romanowicz. Vol. 2 2004. pp. 33-36
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