@inproceedings{cabd41b4f62c490698e50b988c5ece21,
title = "Hierarchical simulation approaches for the design of ultra-fast amplifier circuits",
abstract = "The silicon-on-insulator (SOI) technology is one of the most promising technologies as the semiconductor industry shifts to 0.13μm and smaller devices. Fully depleted (FD) SOI transistors offer a nearly ideal behavior for application in analog circuits, particularly in high frequency and low power operation. In this work, the design and development of a highly efficient power amplifier circuit is investigated for SOI technology. A fully depleted NMOS SOI transistor is built and characterized, which exhibits TeraHertz cutoff frequencies. The device parameters of this transistor are then extracted to build a compact circuit model for use in the PSPICE circuit simulator. Finally, a low power and high frequency class E power amplifier is designed based on the SOI transistor, and a full analysis of the performance compared to bulk Si technology is performed.",
keywords = "Class, DST, Drift diffusion, FDSOI, Power-added-efficiency",
author = "J. Desai and S. Aboud and P. Chiney and P. Osuch and J. Branlard and Stephen Goodnick and Marco Saraniti",
year = "2004",
month = nov,
day = "2",
language = "English (US)",
isbn = "0972842276",
series = "2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004",
pages = "33--36",
editor = "M. Laudon and B. Romanowicz",
booktitle = "2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004",
note = "2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 ; Conference date: 07-03-2004 Through 11-03-2004",
}