Abstract
The silicon-on-insulator (SOI) technology is one of the most promising technologies as the semiconductor industry shifts to 0.13μm and smaller devices. Fully depleted (FD) SOI transistors offer a nearly ideal behavior for application in analog circuits, particularly in high frequency and low power operation. In this work, the design and development of a highly efficient power amplifier circuit is investigated for SOI technology. A fully depleted NMOS SOI transistor is built and characterized, which exhibits TeraHertz cutoff frequencies. The device parameters of this transistor are then extracted to build a compact circuit model for use in the PSPICE circuit simulator. Finally, a low power and high frequency class E power amplifier is designed based on the SOI transistor, and a full analysis of the performance compared to bulk Si technology is performed.
| Original language | English (US) |
|---|---|
| Title of host publication | 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 |
| Editors | M. Laudon, B. Romanowicz |
| Pages | 33-36 |
| Number of pages | 4 |
| Volume | 2 |
| State | Published - 2004 |
| Event | 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 - Boston, MA, United States Duration: Mar 7 2004 → Mar 11 2004 |
Other
| Other | 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 |
|---|---|
| Country | United States |
| City | Boston, MA |
| Period | 3/7/04 → 3/11/04 |
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Keywords
- Class
- Drift diffusion
- DST
- FDSOI
- Power-added-efficiency
ASJC Scopus subject areas
- Engineering(all)
Cite this
Hierarchical simulation approaches for the design of ultra-fast amplifier circuits. / Desai, J.; Aboud, S.; Chiney, P.; Osuch, P.; Branlard, J.; Goodnick, Stephen; Saraniti, Marco.
2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004. ed. / M. Laudon; B. Romanowicz. Vol. 2 2004. p. 33-36.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Hierarchical simulation approaches for the design of ultra-fast amplifier circuits
AU - Desai, J.
AU - Aboud, S.
AU - Chiney, P.
AU - Osuch, P.
AU - Branlard, J.
AU - Goodnick, Stephen
AU - Saraniti, Marco
PY - 2004
Y1 - 2004
N2 - The silicon-on-insulator (SOI) technology is one of the most promising technologies as the semiconductor industry shifts to 0.13μm and smaller devices. Fully depleted (FD) SOI transistors offer a nearly ideal behavior for application in analog circuits, particularly in high frequency and low power operation. In this work, the design and development of a highly efficient power amplifier circuit is investigated for SOI technology. A fully depleted NMOS SOI transistor is built and characterized, which exhibits TeraHertz cutoff frequencies. The device parameters of this transistor are then extracted to build a compact circuit model for use in the PSPICE circuit simulator. Finally, a low power and high frequency class E power amplifier is designed based on the SOI transistor, and a full analysis of the performance compared to bulk Si technology is performed.
AB - The silicon-on-insulator (SOI) technology is one of the most promising technologies as the semiconductor industry shifts to 0.13μm and smaller devices. Fully depleted (FD) SOI transistors offer a nearly ideal behavior for application in analog circuits, particularly in high frequency and low power operation. In this work, the design and development of a highly efficient power amplifier circuit is investigated for SOI technology. A fully depleted NMOS SOI transistor is built and characterized, which exhibits TeraHertz cutoff frequencies. The device parameters of this transistor are then extracted to build a compact circuit model for use in the PSPICE circuit simulator. Finally, a low power and high frequency class E power amplifier is designed based on the SOI transistor, and a full analysis of the performance compared to bulk Si technology is performed.
KW - Class
KW - Drift diffusion
KW - DST
KW - FDSOI
KW - Power-added-efficiency
UR - http://www.scopus.com/inward/record.url?scp=6344249082&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=6344249082&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:6344249082
SN - 0972842276
VL - 2
SP - 33
EP - 36
BT - 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
A2 - Laudon, M.
A2 - Romanowicz, B.
ER -