Hierarchical modeling of phase change memory for reliable design

Zihan Xu; Ketul B. Sutaria; Chengen Yang; Chaitali Chakrabarti; Yu Cao

doi:10.1109/ICCD.2012.6378626

Hierarchical modeling of phase change memory for reliable design

Zihan Xu, Ketul B. Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.

Original language	English (US)
Title of host publication	2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Pages	115-120
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2012.6378626
State	Published - Dec 1 2012
Event	2012 IEEE 30th International Conference on Computer Design, ICCD 2012 - Montreal, QC, Canada Duration: Sep 30 2012 → Oct 3 2012

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)	1063-6404

Other

Other	2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Country/Territory	Canada
City	Montreal, QC
Period	9/30/12 → 10/3/12

Keywords

Hierarchical model
PRAM
Reliability
State Transition Curve
Variability

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2012.6378626

Cite this

Xu, Z., Sutaria, K. B., Yang, C., Chakrabarti, C., & Cao, Y. (2012). Hierarchical modeling of phase change memory for reliable design. In 2012 IEEE 30th International Conference on Computer Design, ICCD 2012 (pp. 115-120). [6378626] (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2012.6378626

Hierarchical modeling of phase change memory for reliable design. / Xu, Zihan; Sutaria, Ketul B.; Yang, Chengen et al.
2012 IEEE 30th International Conference on Computer Design, ICCD 2012. 2012. p. 115-120 6378626 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Xu, Z, Sutaria, KB, Yang, C, Chakrabarti, C & Cao, Y 2012, Hierarchical modeling of phase change memory for reliable design. in 2012 IEEE 30th International Conference on Computer Design, ICCD 2012., 6378626, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 115-120, 2012 IEEE 30th International Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, 9/30/12. https://doi.org/10.1109/ICCD.2012.6378626

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abstract = "As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.",

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AB - As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.

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Hierarchical modeling of phase change memory for reliable design

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Keywords

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