Hierarchical modeling of phase change memory for reliable design

Zihan Xu, Ketul B. Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages115-120
Number of pages6
DOIs
Publication statusPublished - 2012
Event2012 IEEE 30th International Conference on Computer Design, ICCD 2012 - Montreal, QC, Canada
Duration: Sep 30 2012Oct 3 2012

Other

Other2012 IEEE 30th International Conference on Computer Design, ICCD 2012
CountryCanada
CityMontreal, QC
Period9/30/1210/3/12

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Keywords

  • Hierarchical model
  • PRAM
  • Reliability
  • State Transition Curve
  • Variability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Xu, Z., Sutaria, K. B., Yang, C., Chakrabarti, C., & Cao, Y. (2012). Hierarchical modeling of phase change memory for reliable design. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 115-120). [6378626] https://doi.org/10.1109/ICCD.2012.6378626