Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

E. Aykut Dengi, Ronald A. Rohrer

Research output: Contribution to journalConference article

14 Scopus citations

Abstract

A hierarchical two-dimensional field solution technique is introduced for capacitance extraction for VLSI interconnect modeling. As a basis for compromise between the efficiency of Boolean rules-based extraction and the accuracy of flat field solution, this hierarchical approach can handle realistic conductor cross-sections and multiple conformal and/or planarized dielectrics.

Original languageEnglish (US)
Pages (from-to)127-132
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - Jan 1 1997
EventProceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA
Duration: Jun 9 1997Jun 13 1997

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Fingerprint Dive into the research topics of 'Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling'. Together they form a unique fingerprint.

  • Cite this