TY - GEN
T1 - HielM
T2 - 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
AU - Parveen, Farhana
AU - He, Zhezhi
AU - Angizi, Shaahin
AU - Fan, Deliang
N1 - Funding Information:
This material is based upon work supported in part by the National Science Foundation under Grant No. 1740126.
Funding Information:
VII. CONCLUSION In this paper we have proposed a dual-mode in-memory computing architecture using STT-MRAM array architecture which can perform any Boolean logic function (AND/NAND, OR/NOR, XOR/XNOR) between any two memory cells within the same sub-array. Extensive device, circuit and system level simulation have been carried out to evaluate the performance of the proposed in-memory computing platform in both memory mode and computing mode. In-memory bulk bitwise Boolean vector logic (AND/OR) operation for different vector datasets shows ∼ 8× energy saving and ∼ 5× speed up compared to that using DRAM based in-memory computing platform. We further have employed in-memory data encryption engine using AES algorithm, which shows 51.5% and 68.9% lower energy consumption compared to CMOS-ASIC and CMOL based implementations, respectively. To summarize, by adding several significant features as-non-volatility, in-memory logic operation with high data mapping flexibility, low dynamic power consumption, high packing density; our proposed design can thrive a new paradigm for future power efficient in-memory computing platform. ACKNOWLEDGEMENT This material is based upon work supported in part by the National Science Foundation under Grant No. 1740126. REFERENCES
Publisher Copyright:
© 2018 IEEE.
PY - 2018/2/20
Y1 - 2018/2/20
N2 - In this paper we propose a Highly Flexible InMemory (HieIM) computing platform using STT MRAM, which can be leveraged to implement Boolean logic functions without sacrificing memory functionality. It could pre-process data within memory to further reduce power hungry long distance communication between memory and processing units as in Von-Neumann computing system. HieIM can implement all the Boolean logic functions (AND/NAND, OR/NOR, XOR/XNOR) between any two cells in the same memory array, thus overcoming the 'operand locality' problem in contemporary in-memory computing platform designs. To investigate the performance of HieIM, we test in-memory bulk bit-wise Boolean logic operations using different vector datasets, which shows ∼ 8x energy saving and ∼ 5x speedup compared to recent DRAM based in-memory computing platform. We further implement an in-memory data encryption engine design based on HieIM as another case study. With AES algorithm, it shows 51.5% and 68.9% lower energy consumption compared to CMOS-ASIC and CMOL based implementations, respectively.
AB - In this paper we propose a Highly Flexible InMemory (HieIM) computing platform using STT MRAM, which can be leveraged to implement Boolean logic functions without sacrificing memory functionality. It could pre-process data within memory to further reduce power hungry long distance communication between memory and processing units as in Von-Neumann computing system. HieIM can implement all the Boolean logic functions (AND/NAND, OR/NOR, XOR/XNOR) between any two cells in the same memory array, thus overcoming the 'operand locality' problem in contemporary in-memory computing platform designs. To investigate the performance of HieIM, we test in-memory bulk bit-wise Boolean logic operations using different vector datasets, which shows ∼ 8x energy saving and ∼ 5x speedup compared to recent DRAM based in-memory computing platform. We further implement an in-memory data encryption engine design based on HieIM as another case study. With AES algorithm, it shows 51.5% and 68.9% lower energy consumption compared to CMOS-ASIC and CMOL based implementations, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85045308287&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85045308287&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2018.8297350
DO - 10.1109/ASPDAC.2018.8297350
M3 - Conference contribution
AN - SCOPUS:85045308287
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 361
EP - 366
BT - ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 22 January 2018 through 25 January 2018
ER -