Heterogeneous FPGA Architecture using Threshold Logic Gates for Improved Area, Power, and Performance

Ankit Wagle, Sarma Vrudhula

Research output: Contribution to journalArticlepeer-review

Abstract

The flexibility of Field Programmable Gate Arrays (FPGAs) is attributed to the reconfigurability of their Basic Logic Elements (BLEs). Traditionally, the BLEs are comprised of one or more lookup tables (LUT) of n inputs, that are designed to implement Boolean functions of n or fewer inputs. In an attempt to reduce the area and power consumption that comes from using LUTs, a number of complex LUT architectures have been reported. Although most of the proposed complex LUT architectures have resulted in reduced area and power, this has always been at cost of decreased performance. This paper proposes a new FPGA architecture, called TLFPGA, which results in significant improvement in performance, power, and area (PPA). TLFPGA is comprised of a combination of LUTs and a new type of BLE referred to as a threshold logic cell (TLC) muroga. Although TLCs implement a relatively small subset of Boolean functions known as threshold functions muroga, they require far fewer registers and multiplexers than an LUT, and are also significantly faster. The paper describes the architecture of the TLFPGA and a technology mapping algorithm tailored for a TLFGA. On average, TLFPGA designs use 18% fewer registers and multiplexers, which improves the collective area of BLEs by approximately 16%, power by 14%, and performance by 5%. The improvements have been demonstrated in both 40nm and 28nm technologies for ISCAS-85 circuits as well as practical circuits, using industry-standard flows. The improvements were also demonstrated using a layout of the architecture.

Keywords

  • 28nm
  • 40nm
  • Benchmark testing
  • Computer architecture
  • Delays
  • FDSOI
  • Field programmable gate arrays
  • FPGA
  • high performance
  • Integrated circuit interconnections
  • logic decomposition
  • low area
  • low power
  • Magnetic tunneling
  • neuron
  • perceptron
  • PNAND
  • reconfigurable
  • Table lookup
  • technology mapping.
  • Threshold Logic

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Heterogeneous FPGA Architecture using Threshold Logic Gates for Improved Area, Power, and Performance'. Together they form a unique fingerprint.

Cite this