TY - GEN
T1 - Hermes
T2 - 10th IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
AU - Kinsy, Michel A.
AU - Khadka, Shreeya
AU - Isakov, Mihailo
AU - Farrukh, Anam
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/16
Y1 - 2017/6/16
N2 - The emergence of general-purpose system-on-chip (SoC) architectures has given rise to a number of significant security challenges. The current trend in SoC design is system-level integration of heterogeneous technologies consisting of a large number of processing elements such as programmable RISC cores, memory, DSPs, and accelerator function units/ASIC. These processing elements may come from different providers, and application executable code may have varying levels of trust. Some of the pressing architecture design questions are: (1) how to implement multi-level user-defined security; (2) how to optimally and securely share resources and data among processing elements. In this work, we develop a secure multicore architecture, named Hermes. It represents a new architectural framework that integrates multiple processing elements (called tenants) of secure and non-secure cores into the same chip design while (a) maintaining individual tenant security, (b) preventing data leakage and corruption, and (c) promoting collaboration among the tenants. The Hermes architecture is based on a programmable secure router interface and a trust-aware routing algorithm. With 17% hardware overhead, it enables the implementation of processing-element-oblivious secure multicore systems with a programmable distributed group key management scheme.
AB - The emergence of general-purpose system-on-chip (SoC) architectures has given rise to a number of significant security challenges. The current trend in SoC design is system-level integration of heterogeneous technologies consisting of a large number of processing elements such as programmable RISC cores, memory, DSPs, and accelerator function units/ASIC. These processing elements may come from different providers, and application executable code may have varying levels of trust. Some of the pressing architecture design questions are: (1) how to implement multi-level user-defined security; (2) how to optimally and securely share resources and data among processing elements. In this work, we develop a secure multicore architecture, named Hermes. It represents a new architectural framework that integrates multiple processing elements (called tenants) of secure and non-secure cores into the same chip design while (a) maintaining individual tenant security, (b) preventing data leakage and corruption, and (c) promoting collaboration among the tenants. The Hermes architecture is based on a programmable secure router interface and a trust-aware routing algorithm. With 17% hardware overhead, it enables the implementation of processing-element-oblivious secure multicore systems with a programmable distributed group key management scheme.
UR - http://www.scopus.com/inward/record.url?scp=85025126060&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85025126060&partnerID=8YFLogxK
U2 - 10.1109/HST.2017.7951731
DO - 10.1109/HST.2017.7951731
M3 - Conference contribution
AN - SCOPUS:85025126060
T3 - Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
SP - 14
EP - 20
BT - Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 1 May 2017 through 5 May 2017
ER -