Heracles: A tool for fast RTL-based design space exploration of multicore processors

Michel A. Kinsy, Michael Pellauer, Srinivas Devadas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Scopus citations

Abstract

This paper presents Heracles, an open-source, functional, parameterized, synthesizable multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. The Heracles toolkit comprises the soft hardware (HDL) modules, application compiler, and graphical user interface. It is designed with a high degree of modularity to support fast exploration of future multicore processors of different topologies, routing schemes, processing elements (cores), and memory system organizations. It is a component-based framework with parameterized interfaces and strong emphasis on module reusability. The compiler toolchain is used to map C or C++ based applications onto the processing units. The GUI allows the user to quickly configure and launch a system instance for easy factorial development and evaluation. Hardware modules are implemented in synthesizable Verilog and are FPGA platform independent. The Heracles tool is freely available under the open-source MIT license at: http://projects.csail.mit.edu/heracles.

Original languageEnglish (US)
Title of host publicationFPGA 2013 - Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Pages125-134
Number of pages10
DOIs
StatePublished - 2013
Externally publishedYes
Event2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013 - Monterey, CA, United States
Duration: Feb 11 2013Feb 13 2013

Publication series

NameACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Conference

Conference2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2013
Country/TerritoryUnited States
CityMonterey, CA
Period2/11/132/13/13

Keywords

  • distributed shared memory
  • FPGA
  • hardware migration
  • hardware multi-threading
  • mips architectures
  • multicore architecture design
  • network-on-chip
  • open-source
  • RTL-design
  • shared-memory
  • verilog
  • virtual channel router

ASJC Scopus subject areas

  • Computer Science(all)

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