Abstract

Heating effects are investigated in dual-gate devices using an in-house thermal particle-based device simulator. Our simulation results demonstrate that the dual-gate structure is advantageous even though there is slightly higher current degradation due to lattice heating compared to conventional single gate structures, since the magnitude of the on-current is 1.5-1.8 times larger in this structure. Thus, one can trade off a slight increase in current degradation due to lattice heating for more current drive.

Original languageEnglish (US)
Title of host publication2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
Pages10-13
Number of pages4
DOIs
StatePublished - Nov 10 2008
Event2008 8th IEEE Conference on Nanotechnology, IEEE-NANO - Arlington, TX, United States
Duration: Aug 18 2008Aug 21 2008

Publication series

Name2008 8th IEEE Conference on Nanotechnology, IEEE-NANO

Other

Other2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
CountryUnited States
CityArlington, TX
Period8/18/088/21/08

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Goodnick, S., Raleva, K., & Vasileska, D. (2008). Heating effects in dual-gate devices. In 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO (pp. 10-13). [4616994] (2008 8th IEEE Conference on Nanotechnology, IEEE-NANO). https://doi.org/10.1109/NANO.2008.12