TY - GEN
T1 - Heating effects in dual-gate devices
AU - Goodnick, Stephen
AU - Raleva, K.
AU - Vasileska, Dragica
PY - 2008
Y1 - 2008
N2 - Heating effects are investigated in dual-gate devices using an in-house thermal particle-based device simulator. Our simulation results demonstrate that the dual-gate structure is advantageous even though there is slightly higher current degradation due to lattice heating compared to conventional single gate structures, since the magnitude of the on-current is 1.5-1.8 times larger in this structure. Thus, one can trade off a slight increase in current degradation due to lattice heating for more current drive.
AB - Heating effects are investigated in dual-gate devices using an in-house thermal particle-based device simulator. Our simulation results demonstrate that the dual-gate structure is advantageous even though there is slightly higher current degradation due to lattice heating compared to conventional single gate structures, since the magnitude of the on-current is 1.5-1.8 times larger in this structure. Thus, one can trade off a slight increase in current degradation due to lattice heating for more current drive.
UR - http://www.scopus.com/inward/record.url?scp=55349086912&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=55349086912&partnerID=8YFLogxK
U2 - 10.1109/NANO.2008.12
DO - 10.1109/NANO.2008.12
M3 - Conference contribution
AN - SCOPUS:55349086912
SN - 9781424421046
T3 - 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
SP - 10
EP - 13
BT - 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
T2 - 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
Y2 - 18 August 2008 through 21 August 2008
ER -