HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing

Michael Pellauer, Michael Adler, Michel Kinsy, Angshuman Parashar, Joel Emer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

73 Scopus citations

Abstract

In this paper we present the HAsim FPGA-accelerated simulator. HAsim is able to model a shared-memory multicore system including detailed core pipelines, cache hierarchy, and on-chip network, using a single FPGA. We describe the scaling techniques that make this possible, including novel uses of time-multiplexing in the core pipeline and on-chip network. We compare our time-multiplexed approach to a direct implementation, and present a case study that motivates why high-detail simulations should continue to play a role in the architectural exploration process.

Original languageEnglish (US)
Title of host publicationProceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Pages406-417
Number of pages12
DOIs
StatePublished - 2011
Externally publishedYes
Event17th International Symposium on High-Performance Computer Architecture, HPCA 2011 - San Antonio, TX, United States
Duration: Feb 12 2011Feb 16 2011

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Conference

Conference17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Country/TerritoryUnited States
CitySan Antonio, TX
Period2/12/112/16/11

Keywords

  • Field-Programmable Gate Arrays
  • FPGA
  • Modeling
  • On-Chip Networks
  • Simulation

ASJC Scopus subject areas

  • Hardware and Architecture

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