Hardware-software codesign for dynamically reconfigurable architectures

Karam S. Chatha, Ranga Vemuri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

The paper addresses the problem of mapping an application specified as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconfigurable hardware coprocessor and memory elements. The problem comprises of three sub-problems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to different temporal segments and scheduling task execution, reconfiguration of hardware, inter-processor and intra-processor communication. We present a heuristic based technique for solving the problem. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs.

Original languageEnglish (US)
Title of host publicationField Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings
EditorsPatrick Lysaght, James Irvine, Reiner W. Hartenstein
PublisherSpringer Verlag
Pages175-185
Number of pages11
ISBN (Print)3540664572, 9783540664574
DOIs
StatePublished - 1999
Event9th International Workshop on Field Programmable Logic and Applications, FPL 1999 - Glasgow, United Kingdom
Duration: Aug 30 1999Sep 1 1999

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1673
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other9th International Workshop on Field Programmable Logic and Applications, FPL 1999
Country/TerritoryUnited Kingdom
CityGlasgow
Period8/30/999/1/99

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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