Hardware implementation of a neural network pattern shaper algorithm

Electrical stimulation can be used to activate paralyzed muscles for the purpose of restoring motor functions such as stepping in individuals with spinal cord injury. Due to the variability observed in the responses of electrically stimulated muscles, several adaptive control techniques have been developed. The Pattern Shaper (PS) is an adaptive neural network that has been tested in a software implementation and has been shown to be capable of automatically generating cyclic patterns that are customized for an individual. The results of these tests are encouraging, but implementation of the real-time algorithm currently requires a dedicated PC. The purpose of this research is to develop a hardware implementation of a digital PS neural network to generate the electrical signals to stimulate muscles in individuals with spinal cord injury. In this work we have implemented the Pattern Shaper algorithm in hardware by mapping the digital logic circuit to a Field Programmable Gate Array (FPGA), developed a user interface to input data to the FPGA from a computer, and constructed a wire-wrapped board to implement the PS in hardware for use in clinical tests. This hardware implementation is a step towards the development of low-power, portable, adaptive controller that can be used in electrical stimulation systems.