Abstract

Hardware-aware compilers are in high demand for embedded systems with stringent multidimensional design constraints on cost, power, performance, etc. By making use of the microarchitectural information about a processor, a hardware-aware compiler can generate more efficient code than a generic compiler while meeting the design constraints, by exploiting those highly customized microarchitectural features. In this chapter, we introduce two applications of hardware-aware compilers: a hardware-aware compiler can be used as a production compiler and as a tool to efficiently explore the design space of embedded processors. We demonstrate the first application with a compiler that generates efficient code for embedded processors that do not have any branch predictor to reduce branch penalties. To demonstrate the second application, we show how a hardware-aware compiler can be used to explore the Design Space of the bypass designs in the processor. In both the cases, the hardware-aware compiler can generate better code than a hardware-ignorant compiler.

Original languageEnglish (US)
Title of host publicationHandbook of Hardware/Software Codesign
PublisherSpringer Netherlands
Pages795-827
Number of pages33
ISBN (Electronic)9789401772679
ISBN (Print)9789401772662
DOIs
StatePublished - Nov 1 2017

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ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

Cite this

Shrivastava, A., & Cai, J. (2017). Hardware-aware compilation. In Handbook of Hardware/Software Codesign (pp. 795-827). Springer Netherlands. https://doi.org/10.1007/978-94-017-7267-9_26