Abstract

Hardware-aware compilers are in high demand for embedded systems with stringent multidimensional design constraints on cost, power, performance, etc. By making use of the microarchitectural information about a processor, a hardware-aware compiler can generate more efficient code than a generic compiler while meeting the design constraints, by exploiting those highly customized microarchitectural features. In this chapter, we introduce two applications of hardware-aware compilers: a hardware-aware compiler can be used as a production compiler and as a tool to efficiently explore the design space of embedded processors. We demonstrate the first application with a compiler that generates efficient code for embedded processors that do not have any branch predictor to reduce branch penalties. To demonstrate the second application, we show how a hardware-aware compiler can be used to explore the Design Space of the bypass designs in the processor. In both the cases, the hardware-aware compiler can generate better code than a hardware-ignorant compiler.

Original languageEnglish (US)
Title of host publicationHandbook of Hardware/Software Codesign
PublisherSpringer Netherlands
Pages795-827
Number of pages33
ISBN (Electronic)9789401772679
ISBN (Print)9789401772662
DOIs
StatePublished - Nov 1 2017

Fingerprint

Hardware
Embedded systems
Computer hardware
Costs

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

Cite this

Shrivastava, A., & Cai, J. (2017). Hardware-aware compilation. In Handbook of Hardware/Software Codesign (pp. 795-827). Springer Netherlands. https://doi.org/10.1007/978-94-017-7267-9_26

Hardware-aware compilation. / Shrivastava, Aviral; Cai, Jian.

Handbook of Hardware/Software Codesign. Springer Netherlands, 2017. p. 795-827.

Research output: Chapter in Book/Report/Conference proceedingChapter

Shrivastava, A & Cai, J 2017, Hardware-aware compilation. in Handbook of Hardware/Software Codesign. Springer Netherlands, pp. 795-827. https://doi.org/10.1007/978-94-017-7267-9_26
Shrivastava A, Cai J. Hardware-aware compilation. In Handbook of Hardware/Software Codesign. Springer Netherlands. 2017. p. 795-827 https://doi.org/10.1007/978-94-017-7267-9_26
Shrivastava, Aviral ; Cai, Jian. / Hardware-aware compilation. Handbook of Hardware/Software Codesign. Springer Netherlands, 2017. pp. 795-827
@inbook{6da76b91dca5484d8e2c66990ec3b6ad,
title = "Hardware-aware compilation",
abstract = "Hardware-aware compilers are in high demand for embedded systems with stringent multidimensional design constraints on cost, power, performance, etc. By making use of the microarchitectural information about a processor, a hardware-aware compiler can generate more efficient code than a generic compiler while meeting the design constraints, by exploiting those highly customized microarchitectural features. In this chapter, we introduce two applications of hardware-aware compilers: a hardware-aware compiler can be used as a production compiler and as a tool to efficiently explore the design space of embedded processors. We demonstrate the first application with a compiler that generates efficient code for embedded processors that do not have any branch predictor to reduce branch penalties. To demonstrate the second application, we show how a hardware-aware compiler can be used to explore the Design Space of the bypass designs in the processor. In both the cases, the hardware-aware compiler can generate better code than a hardware-ignorant compiler.",
author = "Aviral Shrivastava and Jian Cai",
year = "2017",
month = "11",
day = "1",
doi = "10.1007/978-94-017-7267-9_26",
language = "English (US)",
isbn = "9789401772662",
pages = "795--827",
booktitle = "Handbook of Hardware/Software Codesign",
publisher = "Springer Netherlands",
address = "Netherlands",

}

TY - CHAP

T1 - Hardware-aware compilation

AU - Shrivastava, Aviral

AU - Cai, Jian

PY - 2017/11/1

Y1 - 2017/11/1

N2 - Hardware-aware compilers are in high demand for embedded systems with stringent multidimensional design constraints on cost, power, performance, etc. By making use of the microarchitectural information about a processor, a hardware-aware compiler can generate more efficient code than a generic compiler while meeting the design constraints, by exploiting those highly customized microarchitectural features. In this chapter, we introduce two applications of hardware-aware compilers: a hardware-aware compiler can be used as a production compiler and as a tool to efficiently explore the design space of embedded processors. We demonstrate the first application with a compiler that generates efficient code for embedded processors that do not have any branch predictor to reduce branch penalties. To demonstrate the second application, we show how a hardware-aware compiler can be used to explore the Design Space of the bypass designs in the processor. In both the cases, the hardware-aware compiler can generate better code than a hardware-ignorant compiler.

AB - Hardware-aware compilers are in high demand for embedded systems with stringent multidimensional design constraints on cost, power, performance, etc. By making use of the microarchitectural information about a processor, a hardware-aware compiler can generate more efficient code than a generic compiler while meeting the design constraints, by exploiting those highly customized microarchitectural features. In this chapter, we introduce two applications of hardware-aware compilers: a hardware-aware compiler can be used as a production compiler and as a tool to efficiently explore the design space of embedded processors. We demonstrate the first application with a compiler that generates efficient code for embedded processors that do not have any branch predictor to reduce branch penalties. To demonstrate the second application, we show how a hardware-aware compiler can be used to explore the Design Space of the bypass designs in the processor. In both the cases, the hardware-aware compiler can generate better code than a hardware-ignorant compiler.

UR - http://www.scopus.com/inward/record.url?scp=85035359201&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85035359201&partnerID=8YFLogxK

U2 - 10.1007/978-94-017-7267-9_26

DO - 10.1007/978-94-017-7267-9_26

M3 - Chapter

AN - SCOPUS:85035359201

SN - 9789401772662

SP - 795

EP - 827

BT - Handbook of Hardware/Software Codesign

PB - Springer Netherlands

ER -