TY - JOUR
T1 - Hardware-Accelerated Platforms and Infrastructures for Network Functions
T2 - A Survey of Enabling Technologies and Research Studies
AU - Shantharama, Prateek
AU - Thyagaturu, Akhilesh S.
AU - Reisslein, Martin
N1 - Funding Information:
This work was supported by the National Science Foundation under Grant 1716121.
Publisher Copyright:
© 2013 IEEE.
PY - 2020
Y1 - 2020
N2 - In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called 'softwarized NFs' on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardware-based accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.
AB - In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called 'softwarized NFs' on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardware-based accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.
KW - Central processing unit (CPU)
KW - hardware accelerator
KW - interconnect
KW - memory
KW - software defined networking (SDN)
KW - virtualized network function (VNF)
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U2 - 10.1109/ACCESS.2020.3008250
DO - 10.1109/ACCESS.2020.3008250
M3 - Review article
AN - SCOPUS:85089502667
VL - 8
SP - 132021
EP - 132085
JO - IEEE Access
JF - IEEE Access
SN - 2169-3536
M1 - 9137119
ER -