Guidelines to design parity protected write-back L1 data cache

Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Several decades of technology scaling has brought the challenge of soft errors to modern computing systems, and caches are most susceptible to soft errors. While it is straightforward to protect L2 and other lower level caches using error correcting coding (ECC), protecting the L1 data caches poses a challenge. Parity-based protection of L1 data cache is a more power-efficient alternative, however, some questions still linger - How effective is parity protection for caches? How can we design a parity-based L1 data cache so as to maximize the protection achieved? The goal of this paper is to perform a quantitative evaluation of the protection afforded by various parity-protected cache design alternatives, and formulate guidelines for the design of power-efficient and reliable L1 data caches. Towards this goal, this paper develops an algorithm to accurately model the vulnerability of data in caches, in the presence of various configurations of parity protection, and validate it against extensive fault injection campaigns. We find that, (i) checking parity at reads only (and not at writes) provides 11% more protection with 30% lesser power overheads as compared to that at both reads and writes; and (ii) when implementing parity at the word-level granularity for 53% improved protection as compared to block-level parity implementation, the dirty-bits in the cache should also be implemented at the same granularity, otherwise, there is no improvement in protection. We find several popular commercial processors - even the ones specifically designed for reliability - not following these design guidelines, and resulting in sub-optimial designs.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-July
ISBN (Print)9781450335201
DOIs
StatePublished - Jul 24 2015
Event52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 - San Francisco, United States
Duration: Jun 8 2015Jun 12 2015

Other

Other52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
CountryUnited States
CitySan Francisco
Period6/8/156/12/15

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ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Ko, Y., Jeyapaul, R., Kim, Y., Lee, K., & Shrivastava, A. (2015). Guidelines to design parity protected write-back L1 data cache. In Proceedings - Design Automation Conference (Vol. 2015-July). [7167208] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2744769.2744846