Abstract
Technology extrapolation - the calibration and prediction of achievable design in future technology generations - drives the evolution of VLSI system architectures, design methodologies, and design tools. This paper describes initial experiences with development and use of GTX, the MARCO GSRC Technology Extrapolation system. GTX provides a robust, portable framework for interactive specification and comparison of modeling choices, e.g., for predicting system cycle time, die size and power dissipation. We use GTX to reveal surprising levels of uncertainty (modeling and parameter sensitivity) in widely-cited cycle-time models that drive recent roadmaps. We also describe new SOI and bulk device models that have been developed for GTX, as well as studies of power dissipation and delay uncertainty under various implementation assumptions for global interconnects.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - Design Automation Conference |
| Publisher | IEEE |
| Pages | 693-698 |
| Number of pages | 6 |
| State | Published - 2000 |
| Externally published | Yes |
| Event | DAC 2000: 37th Design Automation Conference - Los Angeles, CA, USA Duration: Jun 5 2000 → Jun 9 2000 |
Other
| Other | DAC 2000: 37th Design Automation Conference |
|---|---|
| City | Los Angeles, CA, USA |
| Period | 6/5/00 → 6/9/00 |
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering