Geometric tiling for reducing power consumption in structured matrix operations

G. Chen, L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, Chaitali Chakrabarti, M. Kandemir, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.

Original languageEnglish (US)
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages113-114
Number of pages2
ISBN (Print)0780397819, 9780780397811
DOIs
StatePublished - Jan 1 2006
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: Sep 24 2006Sep 27 2006

Publication series

Name2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period9/24/069/27/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Chen, G., Xue, L., Kim, J., Sobti, K., Deng, L., Sun, X., Pitsianis, N., Chakrabarti, C., Kandemir, M., & Vijaykrishnan, N. (2006). Geometric tiling for reducing power consumption in structured matrix operations. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 113-114). [4063030] (2006 IEEE International Systems-on-Chip Conference, SOC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOCC.2006.283861