Geometric tiling for reducing power consumption in structured matrix operations

G. Chen; L. Xue; J. Kim; K. Sobti; L. Deng; X. Sun; N. Pitsianis; Chaitali Chakrabarti; M. Kandemir; N. Vijaykrishnan

doi:10.1109/SOCC.2006.283861

Geometric tiling for reducing power consumption in structured matrix operations

G. Chen, L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, Chaitali Chakrabarti, M. Kandemir, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.

Original language	English (US)
Title of host publication	2006 IEEE International Systems-on-Chip Conference, SOC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	113-114
Number of pages	2
ISBN (Print)	0780397819, 9780780397811
DOIs	https://doi.org/10.1109/SOCC.2006.283861
State	Published - Jan 1 2006
Event	2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States Duration: Sep 24 2006 → Sep 27 2006

Publication series

Name	2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other	2006 IEEE International Systems-on-Chip Conference, SOC
Country/Territory	United States
City	Austin, TX
Period	9/24/06 → 9/27/06

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/SOCC.2006.283861

Cite this

Chen, G., Xue, L., Kim, J., Sobti, K., Deng, L., Sun, X., Pitsianis, N., Chakrabarti, C., Kandemir, M., & Vijaykrishnan, N. (2006). Geometric tiling for reducing power consumption in structured matrix operations. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 113-114). Article 4063030 (2006 IEEE International Systems-on-Chip Conference, SOC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOCC.2006.283861

Geometric tiling for reducing power consumption in structured matrix operations. / Chen, G.; Xue, L.; Kim, J. et al.
2006 IEEE International Systems-on-Chip Conference, SOC. Institute of Electrical and Electronics Engineers Inc., 2006. p. 113-114 4063030 (2006 IEEE International Systems-on-Chip Conference, SOC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chen, G, Xue, L, Kim, J, Sobti, K, Deng, L, Sun, X, Pitsianis, N, Chakrabarti, C, Kandemir, M & Vijaykrishnan, N 2006, Geometric tiling for reducing power consumption in structured matrix operations. in 2006 IEEE International Systems-on-Chip Conference, SOC., 4063030, 2006 IEEE International Systems-on-Chip Conference, SOC, Institute of Electrical and Electronics Engineers Inc., pp. 113-114, 2006 IEEE International Systems-on-Chip Conference, SOC, Austin, TX, United States, 9/24/06. https://doi.org/10.1109/SOCC.2006.283861

@inproceedings{a8a312c3a49c4a3fb981b5886c8a062f,

title = "Geometric tiling for reducing power consumption in structured matrix operations",

abstract = "This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.",

author = "G. Chen and L. Xue and J. Kim and K. Sobti and L. Deng and X. Sun and N. Pitsianis and Chaitali Chakrabarti and M. Kandemir and N. Vijaykrishnan",

year = "2006",

month = jan,

day = "1",

doi = "10.1109/SOCC.2006.283861",

language = "English (US)",

isbn = "0780397819",

series = "2006 IEEE International Systems-on-Chip Conference, SOC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "113--114",

booktitle = "2006 IEEE International Systems-on-Chip Conference, SOC",

note = "2006 IEEE International Systems-on-Chip Conference, SOC ; Conference date: 24-09-2006 Through 27-09-2006",

}

TY - GEN

T1 - Geometric tiling for reducing power consumption in structured matrix operations

AU - Chen, G.

AU - Xue, L.

AU - Kim, J.

AU - Sobti, K.

AU - Deng, L.

AU - Sun, X.

AU - Pitsianis, N.

AU - Chakrabarti, Chaitali

AU - Kandemir, M.

AU - Vijaykrishnan, N.

PY - 2006/1/1

Y1 - 2006/1/1

N2 - This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.

AB - This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.

UR - http://www.scopus.com/inward/record.url?scp=43749096094&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=43749096094&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2006.283861

DO - 10.1109/SOCC.2006.283861

M3 - Conference contribution

AN - SCOPUS:43749096094

SN - 0780397819

SN - 9780780397811

T3 - 2006 IEEE International Systems-on-Chip Conference, SOC

SP - 113

EP - 114

BT - 2006 IEEE International Systems-on-Chip Conference, SOC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 IEEE International Systems-on-Chip Conference, SOC

Y2 - 24 September 2006 through 27 September 2006

ER -

Geometric tiling for reducing power consumption in structured matrix operations

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this