The Gateway gate array design exercise has been developed for exposing students to as many of the techniques and disciplines of microelectronic design (and gate array technology in particular) as is possible within the constraints of an academic course. The exercise has been streamlined to carry the student through the stages of logic design, circuit design and computer-aided design of an integrated circuit. On completion of the design, each student's chip is manufactured, and packaged chips are then returned to the student for testing. The paper discusses the technology, software and results obtained from the Gateway exercise undertaken by undergraduate students.
|Original language||English (US)|
|Number of pages||6|
|Journal||IEE Proceedings A: Physical Science. Measurement and Instrumentation. Management and Education. Reviews|
|Issue number||9 pt A|
|State||Published - Dec 1984|
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