TY - JOUR
T1 - Gateway
T2 - A teaching exercise in gate-array technology
AU - Jack, M. A.
AU - Robertson, J. M.
PY - 1984/12
Y1 - 1984/12
N2 - The Gateway gate array design exercise has been developed for exposing students to as many of the techniques and disciplines of microelectronic design (and gate array technology in particular) as is possible within the constraints of an academic course. The exercise has been streamlined to carry the student through the stages of logic design, circuit design and computer-aided design of an integrated circuit. On completion of the design, each student's chip is manufactured, and packaged chips are then returned to the student for testing. The paper discusses the technology, software and results obtained from the Gateway exercise undertaken by undergraduate students.
AB - The Gateway gate array design exercise has been developed for exposing students to as many of the techniques and disciplines of microelectronic design (and gate array technology in particular) as is possible within the constraints of an academic course. The exercise has been streamlined to carry the student through the stages of logic design, circuit design and computer-aided design of an integrated circuit. On completion of the design, each student's chip is manufactured, and packaged chips are then returned to the student for testing. The paper discusses the technology, software and results obtained from the Gateway exercise undertaken by undergraduate students.
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U2 - 10.1049/ip-a-1.1984.0103
DO - 10.1049/ip-a-1.1984.0103
M3 - Article
AN - SCOPUS:0021742855
SN - 0143-702X
VL - 131
SP - 722
EP - 727
JO - IEE Proceedings A: Physical Science. Measurement and Instrumentation. Management and Education. Reviews
JF - IEE Proceedings A: Physical Science. Measurement and Instrumentation. Management and Education. Reviews
IS - 9 pt A
ER -