Gate replacement techniques for simultaneous leakage and aging optimization

Wang Yu, Chen Xiaoming, Wang Wenping, Yu Cao, Xie Yuan, Yang Huazhong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, reducing leakage power remains to be one of the design goals. Because both NBTIinduced circuit degradation and standby leakage power have a strong dependency on the input vectors, Input Vector Control (IVC) technique may be adopted to mitigate leakage and NBTI. However, IVC technique is in-effective for larger circuits. Therefore, in this paper, we propose two fast gate replacement algorithms together with optimal input vector selection to simultaneously mitigate leakage power and NBTI induced circuit degradation: Direct Gate Replacement (DGR) algorithm and Divide and Conquer Based Gate Replacement (DCBGR) algorithm. Our experimental results on 20 benchmark circuits at 65nm technology node reveal that: 1) Both DGR and DCBGR algorithms outperform pure IVC about on average 20% for three different object functions: leakage power reduction only, NBTI mitigation only, and leakage/NBTI co-optimization. 2) The DCBGR algorithm leads to better optimization results and save on average 100X runtime compared with the DGR algorithm.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages328-333
Number of pages6
StatePublished - 2009
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, France
Duration: Apr 20 2009Apr 24 2009

Other

Other2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CountryFrance
CityNice
Period4/20/094/24/09

Fingerprint

Aging of materials
Networks (circuits)
Degradation
Negative bias temperature instability

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Yu, W., Xiaoming, C., Wenping, W., Cao, Y., Yuan, X., & Huazhong, Y. (2009). Gate replacement techniques for simultaneous leakage and aging optimization. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 328-333). [5090683]

Gate replacement techniques for simultaneous leakage and aging optimization. / Yu, Wang; Xiaoming, Chen; Wenping, Wang; Cao, Yu; Yuan, Xie; Huazhong, Yang.

Proceedings -Design, Automation and Test in Europe, DATE. 2009. p. 328-333 5090683.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yu, W, Xiaoming, C, Wenping, W, Cao, Y, Yuan, X & Huazhong, Y 2009, Gate replacement techniques for simultaneous leakage and aging optimization. in Proceedings -Design, Automation and Test in Europe, DATE., 5090683, pp. 328-333, 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, Nice, France, 4/20/09.
Yu W, Xiaoming C, Wenping W, Cao Y, Yuan X, Huazhong Y. Gate replacement techniques for simultaneous leakage and aging optimization. In Proceedings -Design, Automation and Test in Europe, DATE. 2009. p. 328-333. 5090683
Yu, Wang ; Xiaoming, Chen ; Wenping, Wang ; Cao, Yu ; Yuan, Xie ; Huazhong, Yang. / Gate replacement techniques for simultaneous leakage and aging optimization. Proceedings -Design, Automation and Test in Europe, DATE. 2009. pp. 328-333
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abstract = "As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, reducing leakage power remains to be one of the design goals. Because both NBTIinduced circuit degradation and standby leakage power have a strong dependency on the input vectors, Input Vector Control (IVC) technique may be adopted to mitigate leakage and NBTI. However, IVC technique is in-effective for larger circuits. Therefore, in this paper, we propose two fast gate replacement algorithms together with optimal input vector selection to simultaneously mitigate leakage power and NBTI induced circuit degradation: Direct Gate Replacement (DGR) algorithm and Divide and Conquer Based Gate Replacement (DCBGR) algorithm. Our experimental results on 20 benchmark circuits at 65nm technology node reveal that: 1) Both DGR and DCBGR algorithms outperform pure IVC about on average 20{\%} for three different object functions: leakage power reduction only, NBTI mitigation only, and leakage/NBTI co-optimization. 2) The DCBGR algorithm leads to better optimization results and save on average 100X runtime compared with the DGR algorithm.",
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