Functional and timing validation of partially bypassed processor pipelines

Zhu Qiang, Aviral Shrivastava, Nikil Dutt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Customizing the bypasses in pipelined processors is an effective and popular means to perform power, performance and complexity trade-offs in embedded systems. However existing techniques are unable to automatically generate test patterns to functionally validate a partially bypassed processor. Manually specifying directed test sequences to validate a partially bypassed processor is not only a complex and cumbersome task, but is also highly error-prone. In this paper we present an automatic directed test generation technique to verify a partially bypassed processor pipeline using a high-level processor description. We define a fault model and coverage metric for a partially bypassed processor pipeline and demonstrate that our technique can fully cover all the faults using 107,074 tests for the Intel XScale processor within 40 minutes. In contrast, randomly generated tests can achieve 100% coverage with 2 million tests after half day. Furthermore, we demonstrate that our technique is able to generate tests for all possible bypass configurations of the Intel XScale processor.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages1164-1169
Number of pages6
DOIs
StatePublished - 2007
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
CountryFrance
CityNice Acropolis
Period4/16/074/20/07

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Pipelines
Embedded systems

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Qiang, Z., Shrivastava, A., & Dutt, N. (2007). Functional and timing validation of partially bypassed processor pipelines. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 1164-1169). [4211962] https://doi.org/10.1109/DATE.2007.364452

Functional and timing validation of partially bypassed processor pipelines. / Qiang, Zhu; Shrivastava, Aviral; Dutt, Nikil.

Proceedings -Design, Automation and Test in Europe, DATE. 2007. p. 1164-1169 4211962.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Qiang, Z, Shrivastava, A & Dutt, N 2007, Functional and timing validation of partially bypassed processor pipelines. in Proceedings -Design, Automation and Test in Europe, DATE., 4211962, pp. 1164-1169, 2007 Design, Automation and Test in Europe Conference and Exhibition, Nice Acropolis, France, 4/16/07. https://doi.org/10.1109/DATE.2007.364452
Qiang Z, Shrivastava A, Dutt N. Functional and timing validation of partially bypassed processor pipelines. In Proceedings -Design, Automation and Test in Europe, DATE. 2007. p. 1164-1169. 4211962 https://doi.org/10.1109/DATE.2007.364452
Qiang, Zhu ; Shrivastava, Aviral ; Dutt, Nikil. / Functional and timing validation of partially bypassed processor pipelines. Proceedings -Design, Automation and Test in Europe, DATE. 2007. pp. 1164-1169
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