Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs

Shimeng Yu, Yuning Zhao, Yuncheng Song, Gang Du, Jinfeng Kang, Ruqi Han, Xiaoyan Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations
Original languageEnglish (US)
Title of host publicationIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs
StatePublished - Dec 1 2008
EventIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States
Duration: Jun 15 2008Jun 16 2008

Publication series

NameIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Other

OtherIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
CountryUnited States
CityHonolulu, HI
Period6/15/086/16/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yu, S., Zhao, Y., Song, Y., Du, G., Kang, J., Han, R., & Liu, X. (2008). Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs. In IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 [5418481] (IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008). https://doi.org/10.1109/SNW.2008.5418481