From feature scale simulation to backend simulation for a 100 nm CMOS process

Fuad Badrieh, Helmut Puchner, Clemens Heitzinger, Alireza Sheikholesiami, Siegfried Selberherr

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The current challenge for TCAD is the prediction of the performance of groups of devices, backends, and - generally speaking - large parts of the final IC, in contrast to the simulation of single devices and their fabrication. This enables one to predictively simulate the performance of the final device depending on different process technologies and parameters, which the simulation of single devices cannot achieve. In this paper, we focus on the simulation of backend, interconnect capacitance, and time delays. To that end, topography simulations of deposition, etching, and CMP processes in the various metal lines are used to build up the backend stack. The output of the feature scale simulations is used as input to a capacitance extraction tool, whose results are made available directly to the circuit designer. We discuss the utilized simulation tools and their integration. The topography simulations were performed by our tool called ELSA (enhanced level set applications) and the subsequent simulations by RAPHAEL. Finally simulation results for a 100 nm process are presented, where the influence of void formation between metal lines profoundly impacts the performance of the whole interconnect stack.

Original languageEnglish (US)
Title of host publicationESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference
EditorsJose Franca, Paulo Freitas
PublisherIEEE Computer Society
Pages441-444
Number of pages4
ISBN (Electronic)0780379993
ISBN (Print)9780780379992
DOIs
StatePublished - Jan 1 2003
Event33rd European Solid-State Device Research Conference, ESSDERC 2003 - Estoril, Portugal
Duration: Sep 16 2003Sep 18 2003

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Other

Other33rd European Solid-State Device Research Conference, ESSDERC 2003
CountryPortugal
CityEstoril
Period9/16/039/18/03

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Badrieh, F., Puchner, H., Heitzinger, C., Sheikholesiami, A., & Selberherr, S. (2003). From feature scale simulation to backend simulation for a 100 nm CMOS process. In J. Franca, & P. Freitas (Eds.), ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference (pp. 441-444). [1256908] (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2003.1256908