TY - GEN
T1 - FPGAs with reconfigurable threshold logic gates for improved performance, power and area
AU - Wagle, Ankit
AU - Yang, Jinghua
AU - Dengi, Enis
AU - Vrudhula, Sarma
N1 - Funding Information:
†We gratefully acknowledge the National Science Foundation for supporting this work under NSF PFI award no. #1701241.
Funding Information:
We gratefully acknowledge the National Science Foundation for supporting this work under NSF PFI award no. #1701241.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/11/9
Y1 - 2018/11/9
N2 - This paper proposes an alternative FPGA tile structure that consists of three traditional LUTs combined with a new reconfigurable threshold logic cell (TLC). The TLC requires only 7 SRAM cells and can be configured to implement one of several threshold functions. The proposed architecture is implemented in a 28nm FDSOI process, and is evaluated on standard benchmark circuits and several large complex function blocks. The results demonstrate an average reduction of 8.9% in register count, 15.4% in multiplexer count, 7% average reduction in Basic Logic Element (BLE) area, and 8.2% average reduction in BLE power, with a maximum decrease in register count up to 64%, BLE multiplexer count up to 68%, BLE Area up to 51.6% and BLE power up to 61.6% without loss in performance. We also show a reduction of 21% in the area of a tile.
AB - This paper proposes an alternative FPGA tile structure that consists of three traditional LUTs combined with a new reconfigurable threshold logic cell (TLC). The TLC requires only 7 SRAM cells and can be configured to implement one of several threshold functions. The proposed architecture is implemented in a 28nm FDSOI process, and is evaluated on standard benchmark circuits and several large complex function blocks. The results demonstrate an average reduction of 8.9% in register count, 15.4% in multiplexer count, 7% average reduction in Basic Logic Element (BLE) area, and 8.2% average reduction in BLE power, with a maximum decrease in register count up to 64%, BLE multiplexer count up to 68%, BLE Area up to 51.6% and BLE power up to 61.6% without loss in performance. We also show a reduction of 21% in the area of a tile.
KW - Threshold Logic, FPGA, Reconfigurable, FDSOI, 28nm, PNAND, Low Power, Low Area, High Performance
UR - http://www.scopus.com/inward/record.url?scp=85060293322&partnerID=8YFLogxK
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U2 - 10.1109/FPL.2018.00051
DO - 10.1109/FPL.2018.00051
M3 - Conference contribution
AN - SCOPUS:85060293322
T3 - Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
SP - 256
EP - 259
BT - Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 28th International Conference on Field-Programmable Logic and Applications, FPL 2018
Y2 - 26 August 2018 through 30 August 2018
ER -