FPGAs with reconfigurable threshold logic gates for improved performance, power and area

Ankit Wagle; Jinghua Yang; Enis Dengi; Sarma Vrudhula

doi:10.1109/FPL.2018.00051

FPGAs with reconfigurable threshold logic gates for improved performance, power and area

Ankit Wagle, Jinghua Yang, Enis Dengi, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

This paper proposes an alternative FPGA tile structure that consists of three traditional LUTs combined with a new reconfigurable threshold logic cell (TLC). The TLC requires only 7 SRAM cells and can be configured to implement one of several threshold functions. The proposed architecture is implemented in a 28nm FDSOI process, and is evaluated on standard benchmark circuits and several large complex function blocks. The results demonstrate an average reduction of 8.9% in register count, 15.4% in multiplexer count, 7% average reduction in Basic Logic Element (BLE) area, and 8.2% average reduction in BLE power, with a maximum decrease in register count up to 64%, BLE multiplexer count up to 68%, BLE Area up to 51.6% and BLE power up to 61.6% without loss in performance. We also show a reduction of 21% in the area of a tile.

Original language	English (US)
Title of host publication	Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	256-259
Number of pages	4
ISBN (Electronic)	9781538685174
DOIs	https://doi.org/10.1109/FPL.2018.00051
State	Published - Nov 9 2018
Event	28th International Conference on Field-Programmable Logic and Applications, FPL 2018 - Dublin, Ireland Duration: Aug 26 2018 → Aug 30 2018

Other

Other	28th International Conference on Field-Programmable Logic and Applications, FPL 2018
Country	Ireland
City	Dublin
Period	8/26/18 → 8/30/18

Keywords

Threshold Logic, FPGA, Reconfigurable, FDSOI, 28nm, PNAND, Low Power, Low Area, High Performance

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Computer Science Applications
Hardware and Architecture
Software

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10.1109/FPL.2018.00051

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FPGAs with reconfigurable threshold logic gates for improved performance, power and area. / Wagle, Ankit; Yang, Jinghua; Dengi, Enis; Vrudhula, Sarma.

Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 256-259 8533505.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wagle, A, Yang, J, Dengi, E & Vrudhula, S 2018, FPGAs with reconfigurable threshold logic gates for improved performance, power and area. in Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018., 8533505, Institute of Electrical and Electronics Engineers Inc., pp. 256-259, 28th International Conference on Field-Programmable Logic and Applications, FPL 2018, Dublin, Ireland, 8/26/18. https://doi.org/10.1109/FPL.2018.00051

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keywords = "Threshold Logic, FPGA, Reconfigurable, FDSOI, 28nm, PNAND, Low Power, Low Area, High Performance",

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