FPGA architecture for 2D discrete fourier transform based on 2D decomposition for large-sized data

Jung Sub Kim, Chi Li Yu, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Applications based on Discrete Fourier Transforms (DFT) are extensively used in various areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have been used for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement the 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex5 devices. For a 2K x 2K input size, the proposed architecture is 1.96x times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.

Original languageEnglish (US)
Title of host publication2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings
Pages121-126
Number of pages6
DOIs
StatePublished - Dec 1 2009
Event2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Tampere, Finland
Duration: Oct 7 2009Oct 9 2009

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2009 IEEE Workshop on Signal Processing Systems, SiPS 2009
CountryFinland
CityTampere
Period10/7/0910/9/09

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

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    Kim, J. S., Yu, C. L., Deng, L., Kestur, S., Narayanan, V., & Chakrabarti, C. (2009). FPGA architecture for 2D discrete fourier transform based on 2D decomposition for large-sized data. In 2009 IEEE Workshop on Signal Processing Systems, SiPS 2009 - Proceedings (pp. 121-126). [5336236] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). https://doi.org/10.1109/SIPS.2009.5336236