One problem this invention addresses is the cost and speed of processing traditional ion cut materials. A second problem this invention addresses is the current limits on device performance accomplished using the ion cut process. The ion cut process is seen as an attractive atlernative to other processes for making heterogeneous devices and structures. The ion cut process is attractive because of the speed of processing and the reduction in process steps as compared with other heterogeneous device processing. As an example, "back etch silicon on insulator (BESOI) technology involves etching away of hundreds of microns of material in order to result in a thin layer of silicon on an insulator. This back etch process results in the waste of most of the donor wafer, and undesireable total thickness variations in the donor layer surface. Using the ion cut process manufacturers greatly speed up their process time, while cutting costs because the ion cut process can reuse the same bulk donor material over and over.Current ion cut technology involves a process of depostiting a thick implant impeding film which may or may not be photo sensitive prior to the implantation step of ion cutting materials; or alternatively, a process of exfoliating the entire implanted layer, followed by etching away material not wanted. Both of the previously stated processes can be used for building devices in heterogeneous systems, for example silicon on insulator technology. Both processes also have edge profiles which can be improved upon. Edge profiling consists of examining the angle that a structure wall makes with the substrate material. In a perfect edge profile, the structure wall makes an angle of 90 degrees with the substrate surface. In depositing a thick implant impeding layer, the thickness of the film means poor edge profiles due to over or under exposure when using photosensitive films. In the post etch process, over etching results in shorting of a transistor, while under etching results in poor device performance.The current proposed invention would improve on both these problems by eliminating the patterning step, which would further drive down manufacturing cotsts, while simultaneously improving edge profiles in transferred materials. Add to this the ability to program structures at the nanometer scale, and the proposed invention would lead to faster, cheaper devices, with improved device densities.
|Original language||English (US)|
|State||Published - Mar 14 2005|