Abstract
Switched-capacitor voltage regulators (SCVRs) are widely used in on-chip power management, due to high step-down efficiency and feasibility of integration. In this work, we present theoretical analysis and optimization methodology for flying and decoupling capacitance values for area-constrained on-chip SCVRs to achieve the highest system-level power efficiency. The proposed models for efficiency and droop voltage are validated with on-chip 2:1 SCVR implementations in both 65nm and 32nm CMOS, which show high model accuracy. The maximum and average error of the predicted optimal ratio between flying and decoupling capacitance are 5% and 1.7%, respectively.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1269-1272 |
| Number of pages | 4 |
| ISBN (Electronic) | 9783981537093 |
| DOIs | |
| State | Published - May 11 2017 |
| Event | 20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland Duration: Mar 27 2017 → Mar 31 2017 |
Other
| Other | 20th Design, Automation and Test in Europe, DATE 2017 |
|---|---|
| Country/Territory | Switzerland |
| City | Swisstech, Lausanne |
| Period | 3/27/17 → 3/31/17 |
Keywords
- Area-constrained power management
- Capacitance optimization
- Integrated voltage regulator
- Power conversion efficiency
- Switched-capacitor voltage converter
- Voltage droop
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality