TY - GEN
T1 - Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators
AU - Mi, Xiaoyang
AU - Moghadam, Hesam Fathi
AU - Seo, Jae-sun
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5/11
Y1 - 2017/5/11
N2 - Switched-capacitor voltage regulators (SCVRs) are widely used in on-chip power management, due to high step-down efficiency and feasibility of integration. In this work, we present theoretical analysis and optimization methodology for flying and decoupling capacitance values for area-constrained on-chip SCVRs to achieve the highest system-level power efficiency. The proposed models for efficiency and droop voltage are validated with on-chip 2:1 SCVR implementations in both 65nm and 32nm CMOS, which show high model accuracy. The maximum and average error of the predicted optimal ratio between flying and decoupling capacitance are 5% and 1.7%, respectively.
AB - Switched-capacitor voltage regulators (SCVRs) are widely used in on-chip power management, due to high step-down efficiency and feasibility of integration. In this work, we present theoretical analysis and optimization methodology for flying and decoupling capacitance values for area-constrained on-chip SCVRs to achieve the highest system-level power efficiency. The proposed models for efficiency and droop voltage are validated with on-chip 2:1 SCVR implementations in both 65nm and 32nm CMOS, which show high model accuracy. The maximum and average error of the predicted optimal ratio between flying and decoupling capacitance are 5% and 1.7%, respectively.
KW - Area-constrained power management
KW - Capacitance optimization
KW - Integrated voltage regulator
KW - Power conversion efficiency
KW - Switched-capacitor voltage converter
KW - Voltage droop
UR - http://www.scopus.com/inward/record.url?scp=85020172303&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85020172303&partnerID=8YFLogxK
U2 - 10.23919/DATE.2017.7927186
DO - 10.23919/DATE.2017.7927186
M3 - Conference contribution
AN - SCOPUS:85020172303
T3 - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
SP - 1269
EP - 1272
BT - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th Design, Automation and Test in Europe, DATE 2017
Y2 - 27 March 2017 through 31 March 2017
ER -