TY - GEN
T1 - Flexible product code-based ECC schemes for MLC NAND Flash memories
AU - Yang, C.
AU - Emre, Y.
AU - Chakrabarti, Chaitali
AU - Mudge, T.
PY - 2011/12/26
Y1 - 2011/12/26
N2 - Error control coding (ECC) is essential for correcting soft errors in Flash memories. In such memories, as the number of erase/program cycles increases over time, the number of errors increases. In this paper we propose a flexible product code based ECC scheme that can support ECC of higher strength when needed. Specifically, we propose product codes which use Reed-Solomon (RS) codes along rows and Hamming codes along columns. When higher ECC is needed, the Hamming code along columns is replaced by two shorter Hamming codes. For instance, when the raw bit error rate increases from 2.2*10 -3 to 4.0*10 -3, the proposed ECC scheme migrates from RS(127, 121) along rows and Hamming(72,64) along columns to RS(127, 121) along rows and two Hamming(39, 32) along columns to achieve the same BER of 10 -6. While the resulting implementation has 12% higher decoding latency, it increases the lifetime of the device significantly.
AB - Error control coding (ECC) is essential for correcting soft errors in Flash memories. In such memories, as the number of erase/program cycles increases over time, the number of errors increases. In this paper we propose a flexible product code based ECC scheme that can support ECC of higher strength when needed. Specifically, we propose product codes which use Reed-Solomon (RS) codes along rows and Hamming codes along columns. When higher ECC is needed, the Hamming code along columns is replaced by two shorter Hamming codes. For instance, when the raw bit error rate increases from 2.2*10 -3 to 4.0*10 -3, the proposed ECC scheme migrates from RS(127, 121) along rows and Hamming(72,64) along columns to RS(127, 121) along rows and two Hamming(39, 32) along columns to achieve the same BER of 10 -6. While the resulting implementation has 12% higher decoding latency, it increases the lifetime of the device significantly.
KW - Flash memories
KW - error correction codes
KW - multi-level cell
KW - product codes
UR - http://www.scopus.com/inward/record.url?scp=84055212815&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84055212815&partnerID=8YFLogxK
U2 - 10.1109/SiPS.2011.6088985
DO - 10.1109/SiPS.2011.6088985
M3 - Conference contribution
AN - SCOPUS:84055212815
SN - 9781457719219
T3 - 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
SP - 255
EP - 260
BT - 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
T2 - 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
Y2 - 4 October 2011 through 7 October 2011
ER -