TY - JOUR
T1 - Finite-point-based transistor model
T2 - A new approach to fast circuit simulation
AU - Chen, Min
AU - Zhao, Wei
AU - Liu, Frank
AU - Cao, Yu
N1 - Funding Information:
Manuscript received December 18, 2007; revised June 02, 2008. First published March 16, 2009; current version published September 23, 2009. This work was supported in part by IBM, in part by Intel, and in part by the National Science Foundation (NSF) under Grant CCF-0546054. M. Chen, W. Zhao, and Y. Cao are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: min.chen@asu.edu). F. Liu is with the IBM Research Laboratory, Austin, TX 78758 USA. Digital Object Identifier 10.1109/TVLSI.2008.2005061
PY - 2009/10
Y1 - 2009/10
N2 - In this paper, a new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both the I-V and C-V characteristics of a transistor, finite data points are identified based on their physical meanings and their importance in circuit operation. The impact of process and design variations is embedded into these key points using analytical expressions. During the simulation, the entire I-V and C-V curves are interpolated from these points with simple polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A to support generic circuit simulators. The accuracy and convergence of the proposed model are comprehensively evaluated through a set of benchmark circuits, including nand, a pass-gate, latches, AOI, ring oscillators, and an adder. Compared to SPICE simulations with the BSIM models, the simulation time can be reduced by 7 × in transient analysis and more than 9 × in Monte-Carlo simulations.
AB - In this paper, a new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both the I-V and C-V characteristics of a transistor, finite data points are identified based on their physical meanings and their importance in circuit operation. The impact of process and design variations is embedded into these key points using analytical expressions. During the simulation, the entire I-V and C-V curves are interpolated from these points with simple polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A to support generic circuit simulators. The accuracy and convergence of the proposed model are comprehensively evaluated through a set of benchmark circuits, including nand, a pass-gate, latches, AOI, ring oscillators, and an adder. Compared to SPICE simulations with the BSIM models, the simulation time can be reduced by 7 × in transient analysis and more than 9 × in Monte-Carlo simulations.
KW - Circuit simulation
KW - Finite-point-based model
KW - Process variation
KW - Speed
KW - Statistical analysis
KW - Transistor model
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U2 - 10.1109/TVLSI.2008.2005061
DO - 10.1109/TVLSI.2008.2005061
M3 - Article
AN - SCOPUS:70349744045
SN - 1063-8210
VL - 17
SP - 1470
EP - 1480
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 10
M1 - 4801560
ER -