TY - GEN
T1 - Fast statistical circuit analysis with finite-point based transistor model
AU - Chen, Min
AU - Zhao, Wei
AU - Liu, Frank
AU - Cao, Yu
PY - 2007
Y1 - 2007
N2 - A new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both I-V and C-V characteristics of a transistor, finite data points are identified by their physical meaning; the impact of process and design variations is embedded into these points as closed-form expressions. Then, the entire I-V and C-V are extrapolated using polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A at 65nm node. Compared to simulations with the BSIM model, the computation time can be reduced by 7x in transient analysis and 9x in Monte-Carlo simulations.
AB - A new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both I-V and C-V characteristics of a transistor, finite data points are identified by their physical meaning; the impact of process and design variations is embedded into these points as closed-form expressions. Then, the entire I-V and C-V are extrapolated using polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A at 65nm node. Compared to simulations with the BSIM model, the computation time can be reduced by 7x in transient analysis and 9x in Monte-Carlo simulations.
UR - http://www.scopus.com/inward/record.url?scp=34548356683&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548356683&partnerID=8YFLogxK
U2 - 10.1109/DATE.2007.364492
DO - 10.1109/DATE.2007.364492
M3 - Conference contribution
AN - SCOPUS:34548356683
SN - 3981080122
SN - 9783981080124
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1391
EP - 1396
BT - Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
T2 - 2007 Design, Automation and Test in Europe Conference and Exhibition
Y2 - 16 April 2007 through 20 April 2007
ER -