Abstract
Motion estimation is a temporal image compression technique where an n × n block of pixels in the current frame of a video sequence is represented by a motion vector with respect to the best matched block in a search area of the previous frame, and the DCT coefficients of the estimated error terms. In this paper, a fast technique for motion estimation is proposed and later mapped onto the SIMD structure of the Computational*RAM (C*RAM). C*RAM is a conventional computer DRAM (or SRAM) with built-in logic circuitry at the sense-amplifier to take advantage of the high on-chip memory bandwidth and massively parallel SIMD (Single-Instruction stream, Multiple-Data stream) operations. The proposed technique, first, attempts to reduce the n-bit grayscale frames into 1-bit binary frames using morphological filters, and to search for motions of the extracted features on the binary frames. While the reduction procedure requires a small percentage of computation using the full grayscale, the search procedure is performed by simple XOR logic operations and 1-b distortion accumulations on the entire search area. The second part of the paper presents the mapping of the proposed technique onto the C*RAM architecture.
Original language | English (US) |
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Pages (from-to) | 108-118 |
Number of pages | 11 |
Journal | Proceedings of SPIE - The International Society for Optical Engineering |
Volume | 3311 |
DOIs | |
State | Published - Dec 1 1998 |
Externally published | Yes |
Event | Multimedia Hardware Architectures 1998 - San Jose, CA, United States Duration: Jan 29 1998 → Jan 30 1998 |
Keywords
- Logic in memory
- Motion Estimation
- Parallel processing
- SIMD architecture
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering